Semiconductor device and skew adjusting method

Abstract

Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.

1. A semiconductor device, in which function circuits composing one function macro are divided and mounted on plural chips, internal clock signals having different phases with one another are generated based on a clock signal to be a reference, one of the generated internal clock signals is selected, and a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using the selected internal clock signal. 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein the test operation is performed by using the internal clock signal sequentially selected one by one from among the internal clock signals, and the internal clock signal verified the normal operation by the test operation is determined to be the clock signal supplied to the function circuits within the chips. 
 
     
     
       3. The semiconductor device according to  claim 1 ,
 wherein the test operation is executed by using a self test circuit. 
 
     
     
       4. The semiconductor device according to  claim 1 ,
 wherein the function circuits are memory control circuits of which at least an address generation portion and a data input/output portion are mounted on the different chips, and 
 wherein a skew between an address signal outputted from the address generation portion and a data signal inputted/outputted to/from the data input/output portion is adjusted by phase adjustments of the clock signals. 
 
     
     
       5. The semiconductor device according to  claim 4 ,
 wherein the test operation is an operation in which a test data is written and read to/from a memory by using a memory self test circuit, and the internal clock signal at the time when the read data and the test data are consistent is determined to be the clock signal supplied to the function circuits within the chips. 
 
     
     
       6. A semiconductor device in which function circuits composing one function macro are divided and mounted on plural chips, comprising:
 a clock generation circuit generating internal clock signals having different phases with one another based on a clock signal to be a reference; 
 a clock selection circuit selecting one of the internal clock signals generated by said clock generation circuit; and 
 a phase adjusting circuit adjusting a phase of a clock signal supplied to the function circuits within the chips based on a result of a test operation performed by using the internal clock signal selected by said clock selection circuit. 
 
     
     
       7. The semiconductor device according to  claim 6 ,
 wherein said clock selection circuit selects the internal clock signal automatically with reference to the result of the test operation. 
 
     
     
       8. The semiconductor device according to  claim 7 ,
 wherein said clock selection circuit sequentially selects the internal clock signals generated by said clock generation circuit one by one until a normal operation is verified at the test operation, and 
 wherein the internal clock signal which is verified the normal operation at the test operation is determined as the clock signal supplied to the function circuits within the chips. 
 
     
     
       9. The semiconductor device according to  claim 6 ,
 further comprising a self test circuit executing the test operation. 
 
     
     
       10. The semiconductor device according to  claim 6 ,
 wherein the function circuits are memory control circuits of which at least an address generation portion and a data input/output portion are mounted on different chips. 
 
     
     
       11. The semiconductor device according to  claim 10 ,
 further comprising a memory self test circuit executing the test operation, and 
 wherein said memory self test circuit includes: 
 a memory access circuit writing a test data to a memory, and thereafter reading the data from a region to which the corresponding writing is performed; and 
 a comparison circuit comparing the data read by the memory access circuit and the test data, and outputting a compared result as the result of the test operation. 
 
     
     
       12. A skew adjusting method of a semiconductor device in which function circuits composing one function macro are divided and mounted on plural chips, said skew adjusting method comprising the steps of:
 generating internal clock signals having different phases with one another based on a clock signal to be a reference; 
 selecting the generated internal clock signal one by one; and 
 performing a test operation by using the selected internal clock signal, and adjusting a phase of a clock signal supplied to the function circuits within the chips based on the result of the test operation. 
 
     
     
       13. The skew adjusting method according to  claim 12 ,
 wherein the function circuits are memory control circuits of which at least an address generation portion and a data input/output portion are mounted on different chips, and 
 wherein the internal clock signal is selected based on the result of the test operation executed by using the memory self test circuit, and the phase of the clock signal supplied to the function circuits within the chips is adjusted.