Pipelined processor method and circuit with interleaving of iterative operations

Abstract

A method of executing an instruction stream in a pipelined execution unit of depth, p, comprises loading the instruction stream; detecting an iteration of an instruction in the loaded instruction stream; interleaving p steams of instances of the instruction in the pipeline; detecting an end of the iteration; and combining results obtained from the p streams after all programmed iterations have completed. A computational circuit comprises a register which can hold a value representing both an operand and result of an iterative operation; a multiplexer having a first input connected to receive the operand from the register, a second input connected to a source of an identify value for the iterative operation, and an output; and an operator circuit having an input connected to receive a value from the multiplexer output, and an output connected to return thee result to the register. A method of executing an instruction stream in a pipelined execution unit comprises providing to the execution unit the instruction stream as a sequence of instruction in natural order absent software scheduling; detecting an iteration of an instruction in the sequence of instruction; and introducing into a pipeline of the pipelined execution unit plural instances of the iterated instruction, each with different data. A method of executing an instruction stream in a pipelined execution unit comprises detecting an iteration of an instruction in the instruction stream; independently executing plural streams of the iterated instruction; and recombining the independently executed plural streams to provide a single result; wherein independently executing and recombining use not more than one destination register and not more than one temporary register. In a programmable data processor including instruction interlocks and including a pipelined computation unit having a pipeline of depth p, a circuit comprises a controller constructed and arranged to detect an iterative computation in an incoming instruction stream.

1. A method of executing an instruction stream in a pipelined execution unit of depth, p, comprising:
 loading the instruction stream; 
 detecting, in control logic, an iteration operation in an instruction in the loaded instruction stream based on the iterated instruction having an operand register and a destination register that are the same and on consecutive instructions having the same destination register; 
 starting iterated instructions from the instruction stream in the pipelined execution unit and overriding a stall requirement based on data-dependence checking, thereby creating p independent threads of the iterated instructions for concurrent execution in the pipelined execution unit, wherein the pipelined execution unit provides intermediate storage for the p threads; 
 detecting an end of the iteration; and 
 combining results obtained from the p threads after all programmed iterations have completed. 
 
   
   
     2. The method of  claim 1 , wherein p is at least 2. 
   
   
     3. The method of  claim 1 , further comprising:
 disabling interlocking for the detected iteration of the instruction. 
 
   
   
     4. The method of  claim 1 , wherein the iteration of the instruction performs an arithmetic accumulation. 
   
   
     5. The method of  claim 1 , wherein the iteration of the instruction performs an arithmetic product. 
   
   
     6. A method of executing an instruction stream in a pipelined execution unit, comprising:
 providing to the execution unit the instruction stream as a sequence of instructions in natural order absent software scheduling; 
 detecting, in control logic, an iteration operation in an instruction in the sequence of instructions based on the iterated instruction having an operand register and a destination register that are the same and on consecutive instructions having the same destination register; 
 introducing into the pipelined execution unit plural iterated instructions, each with different data, thereby creating plural independent threads of the iterated instructions for concurrent execution in the pipelined execution unit; and 
 combining results for each of the plural threads in the pipelined execution unit. 
 
   
   
     7. The method of  claim 6 , further comprising:
 disabling interlocking for the detected iteration of the instruction. 
 
   
   
     8. The method of  claim 6 , wherein the iteration of the instruction performs an arithmetic accumulation. 
   
   
     9. The method of  claim 6 , wherein the iteration of the instruction performs an arithmetic product. 
   
   
     10. In a programmable data processor including instruction interlocks and including a pipelined computation unit having a pipeline of depth p, a circuit comprising:
 a controller constructed and arranged to detect an iterative computation in an incoming instruction stream; the controller comprising a circuit constructed and arranged to detect an instruction having a single register designated as both a source of an operand and a destination for storing a result; a circuit constructed and arranged to detect a break in an iteration; and a circuit that disables read-after-write and write-after-read interlocks. 
 
   
   
     11. The circuit of  claim 10 , wherein the controller is constructed and arranged to interleave up to p independent threads of the iterative computation which are overlapped in the pipeline. 
   
   
     12. The circuit of  claim 11 , the controller further comprising:
 a circuit constructed and arranged to combine p intermediate results from the p threads into a final result. 
 
   
   
     13. The circuit of  claim 12 , further comprising a register T not used for other computation;
 the controller being further constructed and arranged to redirect results to the register T, after detection of the break. 
 
   
   
     14. The circuit of  claim 10 , the controller further comprising:
 a circuit constructed and arranged to redeploy the interlocks after the iteration is completed. 
 
   
   
     15. A method of executing an instruction stream in a pipelined execution unit, comprising:
 detecting an iteration of an instruction in the instruction stream based on the iterated instruction having an operand register and a destination register that are the same and on consecutive instructions having the same destination register 
 concurrently executing plural independent threads of the iterated instruction in the pipelined execution unit without storing intermediate results outside the pipelined execution unit; and 
 recombining the concurrently executed plural independent threads to provide a single result; 
 wherein concurrently executing and recombining use only one destination register and only one temporary register in addition to the pipelined execution unit. 
 
   
   
     16. The method of  claim 15 , further comprising:
 introducing operands whose value is the identity value for the instruction during an initiation phase.