Packet communication system

Abstract

A Packet communication system has a first line interface; a second line interface that accommodates lines slower than lines accommodated by the first line interface; a crossbar switch; and a scheduler that periodically receives packet output requests from the first and second line interfaces and sends grants based on the requests for the crossbar switch to the first and second line interfaces. The link capacity between the first line interface and the crossbar switch is made higher than that between the second line interface and the crossbar switch, whereby a packet communication system capable of accommodating line interfaces with different speeds efficiently can be provided.

1. A packet communication system comprising:
 a first line interface; 
 a second line interface connectable to a line with a speed lower than that of a line connected to the first line interface; 
 a crossbar switch; and 
 a scheduler that receives packet output requests from the first line interface and the second line interface periodically, and sends packet grants for the crossbar switch accordingly to the first and second line interfaces, 
 wherein a link capacity between the first line interface and the crossbar switch is larger than a link capacity between the second line interface and the crossbar switch, and 
 wherein the number of links forming the link capacity between the first line interface and the crossbar switch is greater than the number of links forming the link capacity between the second line interface and the crossbar switch, and 
 wherein said scheduler controls said crossbar switch based on the relative link capacities between the first line interface and the crossbar switch and between the second line interface and the crossbar switch. 
 
   
   
     2. The packet communication system of  claim 1 , wherein the scheduler receives more packet output requests from the first line interface than from the second line interface in the same cycle. 
   
   
     3. The packet communication system of  claim 1 , wherein the ratio of the maximum number of packet output requests received by the scheduler from the first line interface to the maximum number of packet output requests received from the second line interface in the same cycle equals the ratio of the number of links between the first line interface and the crossbar switch to the number of links between the second line interface and the crossbar switch. 
   
   
     4. The packet communication system of  claim 1 , wherein the scheduler receives packet requests of up to the number of links between the first line interface and the crossbar switch from the first line interface, and receives packet requests of up to the number of links between the second line interface and the crossbar switch from the second line interface. 
   
   
     5. The packet communication system of  claim 1 , wherein the scheduler sends more packet grants to the first line interface than to the second line interface. 
   
   
     6. The packet communication system of  claim 1 , wherein the scheduler sends the first line interface a grant of up to a number of packets equal to the number of links between the first line interface and the crossbar switch, and sends the second line interface a grant of up to a number of packets equal to the number of links between the second line interface and the crossbar switch. 
   
   
     7. A packet communication system comprising:
 a plurality of first line interfaces; 
 a plurality of second line interfaces each having a speed equal to n times the speed of one of the plurality of first line interfaces, where n is a number greater than one; 
 a crossbar switch that is connected to the plurality of first line interfaces and the plurality of second line interfaces; 
 a scheduler that periodically receives packet output requests from the plurality of first line interfaces and the plurality of second line interfaces, controls the crossbar switch accordingly, and periodically sends packet grants for the crossbar switch to the plurality of first line interfaces and the plurality of second line interfaces, 
 wherein each of the plurality of second line interfaces is connected to the crossbar switch by a number of links of equal to n times the number of links that provide connections between the plurality of first line interfaces and the crossbar switch, 
 wherein the scheduler controls the crossbar switch in such a way that the ingress of each one of the plurality of first line interfaces is connected to the egress of another one of the first line interfaces or the egress of one of the second line interfaces, and the ingress of each one of the second line interfaces is connected to the egresses of up to n ones of the first line interfaces or the egress of another one of the second line interfaces, and 
 wherein said scheduler controls the crossbar switch based on the relative number of links between each first line interface and the crossbar switch and between each second line interface and the crossbar switch. 
 
   
   
     8. The packet communication system of  claim 7 , wherein the scheduler, in the same cycle, gives grants to the second line interfaces to send out up to n times as many packets as the maximum number of packets granted to the first line interfaces to be sent out to the crossbar switch. 
   
   
     9. The packet communication system of  claim 7 , wherein the ingress and egress of each one of the plurality of first line interfaces are connected to the crossbar switch with a single link each, and
 wherein the ingress and egress of each one of the plurality of second line interfaces are connected to the crossbar switch with n links. 
 
   
   
     10. The packet communication system of  claim 9 , wherein the ingress of each one of the plurality of first line interfaces has a transmitting driver connected to the single link,
 wherein the egress of each one of the plurality of first line interfaces has a receiver that is connected to the single link, 
 wherein the ingress of each one of the plurality of second line interfaces has n transmitting drivers that are connected to the n links, and 
 wherein the egress of each one of the plurality of second line interfaces has n receivers that are connected to the n links. 
 
   
   
     11. A packet communication system comprising:
 a plurality of first line interfaces; 
 a plurality of second line interfaces each having a speed n times higher than the speed of the first line interface; 
 a crossbar switch that connects the plurality of first line interfaces and the plurality of second line interfaces; 
 a scheduler that periodically receives packet output requests from the plurality of first line interfaces and the plurality of second line interfaces, controls the crossbar switch accordingly, and periodically sends grants for the crossbar switch to the plurality of first line interfaces and the plurality of second line interfaces, 
 wherein each of the plurality of first line interfaces is connected to the crossbar switch with a link speed V, 
 wherein each of the plurality of second line interfaces is connected to the crossbar switch with a link speed n×V, where n is a number greater than one, 
 wherein the scheduler controls the crossbar switch in such a way that the ingress of each one of the first line interfaces is connected to the egress of one of the first line interfaces or an egress of one of the second line interfaces and the ingress of each one of the second line interfaces is connected to up to n egresses of the first line interfaces or the egress of another one of the second line interfaces, and 
 wherein the scheduler controls the crossbar switch based on the relative link speeds between each first line interface and the crossbar switch and between each second line interface and the crossbar switch. 
 
   
   
     12. The packet communication system of  claim 11 , wherein the scheduler, in the same cycle, gives grants to the second line interfaces to send up to n times as many packets as the maximum number of packets granted for the first line interfaces to send to the crossbar switch.