Control device for preventing hardware strapping fault of computer system

Abstract

Disclosed is a control device for preventing hardware strapping fault of a computer system. The computer system includes a central processing unit having a first signal pin, an integrated circuit device having at least one hardware strapping pin, and an external device coupled to the computer system and having a second signal pin. The hardware strapping pin is a multiplexing pin that generates a hardware strapping signal to the central processing unit to perform a hardware strapping operation at the time when the system is being powered on and, after the hardware strapping is completed, is connectable to the second signal pin of the external device. The control device includes a hardware strapping fault prevention circuit coupled between the hardware strapping pin of the integrated circuit device and the second signal pin of the external device to isolate the second signal pin of the external device from the first signal pin of the central processing unit at the time when the system is being powered on.

1. A computer system comprising:
 a central processing unit having at least one first signal pin; 
 an integrated circuit device having at least one hardware strapping pin coupled to the first signal pin of the central processing unit; 
 an external device coupled to the computer system and having a second signal pin; 
 the hardware strapping pin of the integrated circuit device being a multiplexing pin that generates a hardware strapping signal to first signal pin of the central processing unit to perform a hardware strapping operation at the time when the system is being powered on and, after the hardware strapping is completed, is connectable to the second signal pin of the external device; and 
 a hardware strapping fault prevention circuit coupled between the hardware strapping pin of the integrated circuit device and the second signal pin of the external device to isolate the second signal pin of the external device from the first signal pin of the central processing unit at the time when the computer system is being powered on. 
 
   
   
     2. The computer system as claimed in  claim 1 , wherein the integrated circuit device comprises a computer bridge having a bus, and wherein the external device comprises an electronic peripheral device connectable to the computer bridge by the bus. 
   
   
     3. The computer system as claimed in  claim 2 , wherein the computer bridge comprises a south bridge that is connected to the external device. 
   
   
     4. The computer system as claimed in  claim 1 , wherein the hardware strapping fault prevention circuit comprises a switching element that, at the time when the system is being powered on and the integrated circuit device is strapping over the central processing unit, isolates the second signal pin of the external device from the first signal pin of the central processing unit to eliminate conflict between the hardware strapping signal and a signal generated during the initialization of the external device. 
   
   
     5. The computer system as claimed in  claim 1 , wherein the hardware strapping fault prevention circuit comprises a buffering resistor having a first end connected to a reference voltage and a second end connected to the hardware strapping pin of the integrated circuit device, the first signal pin of the central processing unit being connected to the reference voltage by a switching element wherein when the integrated circuit device is performing a strapping over the central processing unit at the time that the external device is being initialized, the buffering resistor forces a signal generated by the first signal pin of the central processing unit to quickly convert into high-level or low-level to ensure correct hardware strapping. 
   
   
     6. The computer system as claimed in  claim 5 , wherein the reference voltage is a ground voltage. 
   
   
     7. The computer system as claimed in  claim 5 , wherein the buffering resistor comprises a pull-low resistor. 
   
   
     8. The computer system as claimed in  claim 5 , wherein the buffering resistor comprises a pull-high resistor.