Amplifying apparatus with automatic level controller

Abstract

A window comparator compares a level of an output signal with an attack reference level, and outputs an attack signal based upon an attack reference comparison result signal thus obtained, and compares the output signal level with a recovery reference level, and outputs a recovery signal based upon a recovery reference comparison result signal thus obtained. An attack timing signal generating unit outputs an attack timing signal at first predetermined time intervals. A recovery timing signal generating unit outputs a recovery timing signal at second time intervals which are longer than the first predetermined time interval. An action determining circuit generates a gain reduction signal and a gain increase signal. The amplification gain of the variable gain amplifier is reduced or increased based upon the gain reduction signal or the gain increase signal.

1. An amplifier circuit including a variable gain amplifier having a function of adjustment of an amplification gain according to a gain control signal for amplifying an input signal with the gain thus adjusted, thereby outputting an output signal within a predetermined level, said amplifier circuit comprising:
 a window comparator which compares a level of said output signal (which will be referred to as “output signal level” hereafter) with an attack reference level, and outputs an attack signal based upon an attack reference comparison result signal thus obtained, and which compares said output signal level with a recovery reference level different from said attack reference level, and outputs a recovery signal based upon a recovery reference comparison result signal thus obtained; 
 an attack timing signal generating unit for outputting an attack timing signal at first predetermined time intervals; 
 a recovery timing signal generating unit for outputting a recovery timing signal at second time intervals which are longer than said first predetermined time interval; and 
 an action determining circuit which generates a gain reduction signal for decrementing said amplification gain by a first predetermined gain each time said attack timing signal is generated during output of said attack signal, and generating a gain increase signal for incrementing said amplification gain by a second predetermined gain each time said recovery timing signal is generated during output of said recovery signal, 
 wherein the amplification gain of said variable gain amplifier is reduced or increased based upon said gain reduction signal or said gain increase signal while maintaining said amplification gain in a case that neither said gain reduction signal nor said gain increase signal is output. 
 
   
   
     2. An amplifier circuit according to  claim 1 , wherein said attack reference comparison result signal is held, and the signal thus held is used as said attack signal,
 and wherein said attack signal is reset according to an attack reset signal output at the same time as with said attack timing signal, 
 and wherein said recovery reference comparison result signal is held, and the signal thus held is used as said recovery signal, 
 and wherein said recovery signal is reset according to a recovery reset signal output at the same time as with said recovery timing signal. 
 
   
   
     3. An amplifier circuit according to  claim 2 , wherein in the event that said output signal level is within a range between: a first recovery reference level which is higher than an output signal center level by a first predetermined voltage; and a second recovery reference level which is lower than said output signal center level by said first predetermined voltage, said recovery reference comparison result signal is output,
 and wherein in the event that said output signal level is greater than a first attack reference level which is higher than said first recovery reference level by a second predetermined voltage, or is smaller than a second attack reference level which is lower than said second recovery reference level by said second predetermined voltage, said attack reference comparison result signal is output. 
 
   
   
     4. An amplifier circuit according to  claim 1 , having functions of adjustment of each of: said first predetermined time interval used in said attack timing generating unit; and said second predetermined time interval used in said recovery timing signal generating unit, according to setting values supplied from external circuits. 
   
   
     5. An amplifier circuit according to  claim 2 , having functions of adjustment of each of: said first predetermined time interval used in said attack timing generating unit; and said second predetermined time interval used in said recovery timing signal generating unit, according to setting values supplied from external circuits. 
   
   
     6. An amplifier circuit according to  claim 3 , having functions of adjustment of each of: said first predetermined time interval used in said attack timing generating unit; and said second predetermined time interval used in said recovery timing signal generating unit, according to setting values supplied from external circuits. 
   
   
     7. An amplifier circuit according to  claim 4 , further including a setting circuit for rewritably storing setting values which are supplied from external circuits and used as said first predetermined time interval and said second predetermined time interval,
 wherein said first predetermined time interval and said second predetermined time interval are set in said attack timing signal generating unit and said recovery timing signal generating unit, respectively, based upon said setting values stored in said setting circuit. 
 
   
   
     8. An amplifier circuit according to  claim 5 , further including a setting circuit for rewritably storing setting values which are supplied from external circuits and used as said first predetermined time interval and said second predetermined time interval,
 wherein said first predetermined time interval and said second predetermined time interval are set in said attack timing signal generating unit and said recovery timing signal generating unit, respectively, based upon said setting values stored in said setting circuit. 
 
   
   
     9. An amplifier circuit according to  claim 6 , further including a setting circuit for rewritably storing setting values which are supplied from external circuits and used as said first predetermined time interval and said second predetermined time interval,
 wherein said first predetermined time interval and said second predetermined time interval are set in said attack timing signal generating unit and said recovery timing signal generating unit, respectively, based upon said setting values stored in said setting circuit. 
 
   
   
     10. An amplifier circuit according to  claim 1 , wherein said attack timing signal generating unit and said recovery timing signal generating unit are counter circuits for counting a clock signal supplied from external circuits, thereby counting said first and second predetermined time intervals. 
   
   
     11. An amplifier circuit according to  claim 1 , wherein said variable gain amplifier is of a switched-resistor amplifier type having a function of adjustment of the gain by switching resistance of a resistor included therein,
 and wherein gain control is performed by switching said resistance between multiple values by actions of a set of switches. 
 
   
   
     12. An amplifier circuit according to  claim 2 , wherein said variable gain amplifier is of a switched-resistor amplifier type having a function of adjustment of the gain by switching resistance of a resistor included therein,
 and wherein gain control is performed by switching said resistance between multiple values by actions of a set of switches. 
 
   
   
     13. An amplifier circuit according to  claim 3 , wherein said variable gain amplifier is of a switched-resistor amplifier type having a function of adjustment of the gain by switching resistance of a resistor included therein,
 and wherein gain control is performed by switching said resistance between multiple values by actions of a set of switches. 
 
   
   
     14. An amplifier circuit according to  claim 11 , further including a decoder which generates said gain control signal based upon said gain reduction signal and said gain increase signal, and which supplies said gain control signal to said variable gain amplifier,
 wherein a maximum value and a minimum value of said gain control signal output from said decoder are adjustably set based upon setting values supplied from external circuits. 
 
   
   
     15. An amplifier circuit according to  claim 12 , further including a decoder which generates said gain control signal based upon said gain reduction signal and said gain increase signal, and which supplies said gain control signal to said variable gain amplifier,
 wherein a maximum value and a minimum value of said gain control signal output from said decoder are adjustably set based upon setting values supplied from external circuits. 
 
   
   
     16. An amplifier circuit according to  claim 13 , further including a decoder which generates said gain control signal based upon said gain reduction signal and said gain increase signal, and which supplies said gain control signal to said variable gain amplifier,
 wherein a maximum value and a minimum value of said gain control signal output from said decoder are adjustably set based upon setting values supplied from external circuits. 
 
   
   
     17. An amplifier circuit according to  claim 14 , further including a setting circuit for rewritably storing setting values which are supplied from external circuits, and used as said maximum value and said minimum value of said gain control signal,
 wherein said maximum value and said minimum value of said gain control signal are set in said decoder based upon said setting values stored in said setting circuit. 
 
   
   
     18. An amplifier circuit according to  claim 15 , further including a setting circuit for rewritably storing setting values which are supplied from external circuits, and used as said maximum value and said minimum value of said gain control signal,
 wherein said maximum value and said minimum value of said gain control signal are set in said decoder based upon said setting values stored in said setting circuit. 
 
   
   
     19. An amplifier circuit according to  claim 16 , further including a setting circuit for rewritably storing setting values which are supplied from external circuits, and used as said maximum value and said minimum value of said gain control signal,
 wherein said maximum value and said minimum value of said gain control signal are set in said decoder based upon said setting values stored in said setting circuit. 
 
   
   
     20. An electronic device comprising:
 an audio output unit; and 
 an amplifier circuit according to  claim 1  which output an analog audio signal to said audio output unit.