Dual-mode pulse generator

Abstract

A pulse generator electrical circuit capable of operating as both a clock-based pulse generator and a delay-based pulse generator while minimizing the limitations of these two types of pulse generators is disclosed. When the pulse generator operates in “delay mode,” the smallest output pulse width possible corresponds to the minimum set point delay between the two delay circuits. The largest possible output pulse width corresponds to the difference between the maximum and minimum of the delay circuits. When the pulse generator operates in “clock mode,” the output of one of the delay circuits is blocked so that the output of the gate depends solely on the output of other delay circuit. This limits the lower pulse width interval to that of the retimer clock, but allows for an arbitrarily long (wide) pulse.

1. A pulse generator comprising:
 a clock adapted to generate clock pulses; 
 a phase lock loop (PLL) operably coupled to the clock so that the clock pulses have reduced jitter; 
 a retimer operatively coupled to the clock; 
 first and second delays operatively coupled to an output of the retimer and each having an output; 
 a timing generator operatively coupled to an input of one of the first and second delays; 
 a logic gate coupled to receive the outputs of the first and second delays and adapted to generate an output pulse based on the outputs of the first and second delays; and 
 wherein the timing generator is operatively coupled to the retimer and the retimer retimes clock signals from the timing generator based on the reduced-jitter clock pulses, and wherein the timing generator includes a field-programmable gate array adapted to allow the pulse generator to operate in one of a clock mode and a delay mode. 
 
     
     
       2. The pulse generator of  claim 1 , wherein setting the mode of operation includes the timing generator sending a mode-select control signal to the second delay. 
     
     
       3. The pulse generator of  claim 1 , wherein the FPGA includes registers, and wherein the FPGA is coupled to a controller that inputs values into the registers corresponding to one of the clock mode and delay mode.