Multiple size memories in a programmable logic device

Abstract

Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.

1. An integrated circuit comprising:
 an array of logic elements configurable to implement user-defined logic functions, each logic element including a lookup table, wherein at least one logic element lookup table is further configurable for use as a distributed memory for data storage; 
 a first memory block having a first set of control logic and circuits, the first memory block disposed within the array of logic elements; and 
 a second memory block having a second set of control logic and circuits, the second memory block disposed within the array of logic elements, 
 wherein the first and second memory blocks have different memory sizes. 
 
   
   
     2. The integrated circuit of  claim 1  wherein each logic element lookup table in a logic array block is used to form a distributed memory for data storage. 
   
   
     3. The integrated circuit of  claim 1  further comprising a configuration memory location, wherein the configuration memory location is used for data storage. 
   
   
     4. The integrated circuit of  claim 1  wherein the first memory block is one memory block in a column of memory blocks, each having the same size. 
   
   
     5. The integrated circuit of  claim 4  wherein two of the memory blocks in the column of memory blocks can be combined to form a larger memory. 
   
   
     6. The integrated circuit of  claim 4  wherein a memory block in the column of memory blocks can be combined with a logic element lookup table to form a larger memory. 
   
   
     7. The integrated circuit of  claim 1  further comprising a third memory block having a third set of control logic and circuits, the third memory block disposed within the array of logic elements,
 wherein the first, second, and third memories have different sizes. 
 
   
   
     8. The integrated circuit of  claim 1  wherein the first memory block has a configurable width and a configurable depth. 
   
   
     9. An integrated circuit comprising:
 an array of logic elements arranged in a plurality of logic array blocks and configurable to implement user-defined logic functions, each logic element including at least one lookup table that may be used to form a distributed memory for data storage; 
 a first embedded memory block disposed within the array of logic elements; and 
 at least a second embedded memory block disposed within the array of logic elements, 
 wherein the first memory block has greater memory size than the second embedded memory block. 
 
   
   
     10. The integrated circuit of  claim 9  wherein each logic element lookup table in at least one logic array block can be used to form a distributed memory for data storage. 
   
   
     11. The integrated circuit of  claim 9  further comprising a configuration memory location, wherein the configuration memory location is used for data storage. 
   
   
     12. The integrated circuit of  claim 9  wherein the first embedded memory block is one memory block in a column of memory blocks, each having the same size, where adjacent memory blocks in the column of memory blocks can be combined to form a larger memory. 
   
   
     13. The integrated circuit of  claim 9  further comprising a third embedded memory block, the third embedded memory block disposed within the array of logic elements,
 wherein the first, second, and third embedded memory blocks have different sizes. 
 
   
   
     14. The integrated circuit of  claim 1  wherein the first embedded memory block has a configurable width and a configurable depth. 
   
   
     15. An integrated circuit comprising:
 a plurality of programmable logic elements arranged in a plurality of rows and columns and configurable to implement user-defined logic functions, at least one logic element including a lookup table further configurable to implement a distributed memory for data storage; 
 a first embedded memory coupled to a first set of the plurality of programmable logic elements, the first embedded memory having a first size; and 
 a first plurality of columns of second embedded memories, each second embedded memory having a second size, 
 wherein the first size is larger than the second size. 
 
   
   
     16. The integrated circuit of  claim 15  further comprising:
 a second plurality of columns of third embedded memories, each third embedded memory having a third size, wherein the second size is larger than the third size. 
 
   
   
     17. The integrated circuit of  claim 15  wherein adjacent second embedded memories can be combined to form larger memories. 
   
   
     18. The integrated circuit of  claim 15  wherein a second embedded memory can be combined with a lookup table in a logic element to form a larger memory. 
   
   
     19. The integrated circuit of  claim 15  wherein each logic element lookup table in a logic array block can be used to form a distributed memory for data storage. 
   
   
     20. The integrated circuit of  claim 15  wherein the integrated circuit is a field programmable gate array.