RAKE receiver device

Abstract

A RAKE receiver device includes a plurality of fingers for demodulating multipath receive data, and a data synthesis circuit for synthesizing the receive data from each of the paths and demodulated by the plural fingers. Each time the receive data is demodulated by one of the plural fingers, the data synthesis circuit adds cumulatively the demodulated receive data for each identical receive data from each of the paths, and synthesizes the data.

1. A RAKE receiver device comprising:
 a plurality of fingers for demodulating receive data of multiple paths; 
 a data synthesis circuit for synthesizing the receive data from each of the paths and demodulated by the plurality of fingers; and 
 a timing adjustment circuit for adjusting timing when the receive data from each of the paths and demodulated by the plurality of fingers are provided to the data synthesis circuit, 
 wherein the timing adjustment circuit holds the receive data from each of the paths and demodulated by the fingers, and each time that the receive data from each of the paths are demodulated by the plurality of fingers are supplied from the timing adjustment circuit, the data synthesis circuit adds cumulatively the demodulated receive data for each identical receive data from each of the paths, and synthesizes the data. 
 
   
   
     2. A RAKE receiver device, comprising,
 a plurality of fingers for demodulating receive data of multiple paths; 
 a data synthesis circuit for synthesizing the receive data from each of the paths and demodulated by the plurality of fingers, 
 wherein each time that the receive data from each of the path is demodulated by one of the plurality of fingers, the data synthesis circuit adds cumulatively the demodulated receive data for each identical receive data from each of the paths, and synthesizes the data; and 
 wherein the data synthesis circuit comprises one memory that is shared by the fingers, and each time the receive data from each of the paths are demodulated by the plurality of fingers, cumulatively added data is read out from each corresponding memory address, added to the demodulated identical receive data from each of the paths, and written back into the same respectively corresponding address of the memory. 
 
   
   
     3. A RAKE receiver device, comprising;
 a plurality of fingers for demodulating receive data of multiple paths, 
 wherein the fingers are set in advance with priority order; 
 a data synthesis circuit for synthesizing the receive data from each of the paths and demodulated by the plurality of fingers, 
 wherein each time that the receive data of each path is demodulated by one of the plurality of fingers, the data synthesis circuit adds cumulatively the demodulated receive data for each identical receive data from each of the paths, and synthesizes the data; and 
 wherein the data synthesis circuit adds cumulatively, one at a time and in chronological order, the identical receive data from each of the paths and demodulated by the plurality of fingers, and when two or more demodulated receive data from each of the paths are inputted simultaneously, the data synthesis circuit sequentially adds cumulatively the demodulated receive data from each of the paths for each identical receive data, according to the priority order. 
 
   
   
     4. A RAKE receiver device comprising:
 a plurality of fingers for demodulating receive data from multiple paths; 
 a data synthesis circuit for synthesizing the receive data from each of the paths and demodulated by the plurality of fingers; and 
 a timing adjustment circuit for adjusting timing when the receive data from each of the paths and demodulated by the plurality of fingers are provided to the data synthesis circuit, 
 wherein the plurality of fingers demodulate a plurality of receive data per one symbol time unit, the timing adjustment circuit holds the plurality of receive data from each of the paths and demodulated by the plurality of fingers, and each time that the receive data from each of the paths and demodulated by the plurality of fingers are supplied from the timing adjustment circuit, the data synthesis circuit adds cumulatively the demodulated receive data for each identical receive data from each of the paths, and synthesizes the data. 
 
   
   
     5. A RAKE receiver device according to  claim 4 , wherein the data synthesis circuit comprises one memory shared by the plurality of fingers, each time that the receive data from each of the paths and demodulated by the plurality of fingers are supplied from the timing adjustment circuit, cumulatively added data is read out from each corresponding memory address, added to the demodulated identical receive data from each of the paths, and written back into the same respectively corresponding address of the memory. 
   
   
     6. A RAKE receiver device according to  claim 4 , wherein the plurality of fingers and the plurality of receive data are each set in advance with priority order,
 the data synthesis circuit receives from the timing adjustment circuit the demodulated receive data from each of the paths and adds cumulatively them one at a time and in chronological order, when two or more of the demodulated receive data from each of the paths are held in the timing adjustment circuit, the data synthesis circuit sequentially receives, from the timing adjustment circuit, the same-priority-order demodulated receive data of the plurality of fingers according to the priority order of the fingers, further repeats this operation according to the priority order of the receive data, and sequentially adds cumulatively the demodulated receive data from each of the paths for each identical receive data. 
 
   
   
     7. A RAKE receiver device according to  claim 1 , wherein the data synthesis circuit comprises one memory that is shared by the fingers, and each time the receive data from each of the paths are demodulated by the plurality of fingers, cumulatively added data is read out from each corresponding memory address, added to the demodulated identical receive data from each of the paths, and written back into the same respectively corresponding address of the memory. 
   
   
     8. A RAKE receiver device according to  claim 1 , wherein the fingers are set in advance with priority order,
 the data synthesis circuit adds cumulatively, one at a time and in chronological order, the identical receive data from each of the paths and demodulated by the plurality of fingers, and when two or more demodulated receive data from each of the paths are inputted simultaneously, the data synthesis circuit sequentially adds cumulatively the demodulated receive data from each of the paths for each identical receive data, according to the priority order. 
 
   
   
     9. A RAKE receiver device according to  claim 2 , wherein the fingers are set in advance with priority order,
 the data synthesis circuit adds cumulatively, one at a time and in chronological order, the identical receive data from each of the paths and demodulated by the plurality of fingers, and when two or more demodulated receive data from each of the paths are inputted simultaneously, the data synthesis circuit sequentially adds cumulatively the demodulated receive data from each of the paths for each identical receive data, according to the priority order. 
 
   
   
     10. A RAKE receiver device according to  claim 5 , wherein the plurality of fingers and the plurality of receive data are each set in advance with priority order,
 the data synthesis circuit receives from the timing adjustment circuit the demodulated receive data from each of the paths and adds cumulatively them one at a time and in chronological order, when two or more of the demodulated receive data from each of the paths are held in the timing adjustment circuit, the data synthesis circuit sequentially receives, from the timing adjustment circuit, the same-priority-order demodulated receive data of the plurality of fingers according to the priority order of the fingers, further repeats this operation according to the priority order of the receive data, and sequentially adds cumulatively the demodulated receive data from each of the paths for each identical receive data.