Dynamic programmable logic array having enable unit

Abstract

A DPLA (dynamic programmable logic array) uses an enable unit for each output line that provides OR-functionality, to eliminate a clock signal in the OR-plane. A clock signal is used only in the AND-plane for pre-charging the product term lines. Such a DPLA operates properly without a delay constraint between clock signals in both the AND-plane and the OR-plane for proper operation at higher frequencies.

1. An apparatus for performing a logic function on a plurality of inputs to generate an output, comprising:
 a respective switching device that receives a respective input for each of a first subset of the inputs to set the output to a first output logical state if the respective input is a first input logical state; and 
 an enable unit that receives a second subset of the inputs to set the output to the first output logical state if any input of the second subset is the first input logical state without dependency on any clock signal, 
 wherein the enable unit is connected directly to an output line having the output generated thereon. 
 
   
   
     2. The apparatus of  claim 1 , wherein the enable unit determines a logical state of the output from the second subset of inputs when every input of the first subset is a second input logical state. 
   
   
     3. An apparatus for performing a logic function on a plurality of inputs to generate an output, comprising:
 a respective switching device that receives a respective input for each of a first subset of the inputs to set the output to a first output logical state if the respective input is a first input logical state; and 
 an enable unit that receives a second subset of the inputs to set the output to the first output logical state if any input of the second subset is the first input logical state; 
 wherein the enable unit determines a logical state of the output from the second subset of inputs when every input of the first subset is a second input logical state; 
 and wherein the enable unit is an enable circuit including: 
 a first switching device that turns on to couple a first voltage source to an output line for setting the output to the first output logical state; 
 a second switching device that turns on to couple a second voltage source to the output line for setting the output to the second output logical state; and 
 at least one logic gate for determining which of the first and second switches to turn on from the second subset of the inputs. 
 
   
   
     4. The apparatus of  claim 1 , wherein the first subset and the second subset are mutually exclusive sets of the inputs. 
   
   
     5. The apparatus of  claim 4 , wherein the first subset and the second subset comprise all of the inputs. 
   
   
     6. The apparatus of  claim 5 , wherein the second subset consists of just one of the inputs that is not part of the first subset. 
   
   
     7. The apparatus of  claim 1 , wherein each respective switching device is a MOSFET with a gate coupled to the respective input. 
   
   
     8. The apparatus of  claim 1 , wherein the logic function is an OR function. 
   
   
     9. The apparatus of  claim 8 , wherein the output is generated at an output line of a dynamic PLA (programmable logic array). 
   
   
     10. The apparatus of  claim 9 , wherein each of the inputs is a respective product term from a corresponding product term line of the dynamic PLA. 
   
   
     11. The apparatus of  claim 10 , wherein each product term line is pre-charged to set the output to the first output logical state during a pre-charge time of an AND-plane clock signal. 
   
   
     12. The apparatus of  claim 11 , wherein the enable unit and each respective switching device determine a logical state of the output from the inputs during an evaluation time of the AND-plane clock signal. 
   
   
     13. The apparatus of  claim 9 , wherein the output line is not pre-charged with an OR-plane clock signal. 
   
   
     14. The apparatus of  claim 9 , wherein the output line is not coupled to any OR-plane clock signal. 
   
   
     15. An apparatus for performing a logic function on a plurality of inputs to generate an output, comprising:
 a respective switching device that receives a respective input for each of a first subset of the inputs to set a first pre-output on a first pre-output line to a first output logical state if the respective input is a first input logical state; 
 a first enable unit that receives a second subset of the inputs to set the first pre-output to the first output logical state if any input of the second subset is the first input logical state; 
 a respective switching device that receives a respective input for each of a third subset of the inputs to set a second pre-output on a second pre-output line to the first output logical state if the respective input is the first input logical state; 
 a second enable unit that receives a fourth subset of the inputs to set the second pre-output to the first output logical state if any input of the fourth subset is the first input logical state; and 
 a logic unit for combining the first and second pre-outputs to generate the output. 
 
   
   
     16. The apparatus of  claim 15 , wherein the first enable unit determines a logical state of the first pre-output from the second subset of inputs when every input of the first subset is a second input logical state, and wherein the second enable unit determines a logical state of the second pre-output from the fourth subset of inputs when every input of the third subset is the second input logical state. 
   
   
     17. The apparatus of  claim 15 , wherein the first, second, third, and fourth subsets are mutually exclusive sets of the inputs, and wherein the first, second, third, and fourth subsets comprise all of the inputs,
 and wherein the second subset consists ofjust one of the inputs that is not part of the first, third, and fourth subsets, and wherein the fourth subset consists ofjust one of the inputs that is not part of the first, second, and third subsets. 
 
   
   
     18. The apparatus of  claim 15 , wherein the output is generated at an output line of a dynamic PLA (programmable logic array), and wherein each of the inputs is a respective product term from a corresponding product term line of the dynamic PLA. 
   
   
     19. A dynamic PLA comprising:
 an AND-plane of a plurality of product term lines for providing a plurality of product terms; and 
 an OR plane of at least one output line, each providing an output as an OR-function of respective product terms from the AND-plane, and each including:
 a respective switching device that receives a respective product term for each of a first subset of the product terms to set the output to a first output logical state if the respective product term is a first input logical state; and 
 a respective enable unit that receives a second subset of the product terms to set the output to the first output logical state if any product term of the second subset is the first logical state, 
 wherein the respective enable unit is connected directly to the output line having the output generated thereon. 
 
 
   
   
     20. The dynamic PLA of  claim 19 , wherein the AND-plane receives a clock signal for providing the product terms on the product term lines during an evaluation time of the clock signal after the product term lines are pre-charged during a pre-charge time of the clock signal. 
   
   
     21. The dynamic PLA of  claim 20 , wherein the OR-plane provides the OR-function of the product terms during the evaluation time without pre-charging the output line. 
   
   
     22. The dynamic PLA of  claim 19 , wherein the respective enable unit determines a logical state of the output line from the second subset of product terms when every product term of the first subset is a second input logical state. 
   
   
     23. The dynamic PLA of  claim 22 , wherein the respective enable unit is an enable circuit including:
 a first switching device that turns on to couple a first voltage source to the output line for setting the output to the first output logical state; 
 a second switching device that turns on to couple a second voltage source to the output line for setting the output to the second output logical state; and 
 at least one logic gate for determining which of the first and second switches to turn on from the second subset of product terms. 
 
   
   
     24. The dynamic PLA of  claim 19 , wherein the respective enable unit for each output line receives a different respective selected one of the product terms. 
   
   
     25. The dynamic PLA of  claim 24 , wherein the respective selected one of the product terms received by the respective enable unit is not coupled to any of the respective switching device, for each of the output lines.