Insulated gate bipolar transistor

Abstract

An IGBT includes a plurality of n + doped regions ( 11 ) selectively formed in a main surface ( 103 ) of a p + semiconductor layer ( 12 ) opposite from an n type semiconductor layer ( 80 ) without being connected to the n type semiconductor layer ( 80 ). The n + doped regions ( 11 ) are formed in corresponding relation to and only under channel regions (CH 1 a -CH 1 d ) of structures ( 200 a - 200 d ), respectively. This lowers the effective concentration of the p + semiconductor layer ( 12 ) on the n + doped regions ( 11 ) to reduce the number of holes injected from a collector layer ( 9 ) in an off state, reducing a leakage current.

1. An insulated gate bipolar transistor comprising:
 a first semiconductor layer of a first conductivity type having a first main surface and a second main surface opposite from said first main surface; 
 a second semiconductor layer of a second conductivity type formed on an entire face of said first main surface of said first semiconductor layer; 
 a plurality of first doped regions of said first conductivity type selectively formed in a main surface of said second semiconductor layer opposite from said first semiconductor layer without being connected to said first semiconductor layer; 
 a collector electrode formed on said main surface of said second semiconductor layer to cover an entire surface of each of said first doped regions; and 
 a plurality of structures each including
 a second doped region of said second conductivity type selectively formed in said second main surface of said first semiconductor layer without being connected to said second semiconductor layer, 
 a third doped region of said first conductivity type selectively formed in a surface of said second doped region without being connected to said first semiconductor layer, 
 a channel region defined in a portion of said surface of said second doped region which lies between said third doped region and said first semiconductor layer,
 an insulation film formed on said channel region, 
 a gate electrode formed on said insulation film, and 
 an emitter electrode connected to said second and third doped regions, 
 
 
 wherein said plurality of first doped regions are formed in corresponding relation to and only under said channel regions of said structures, respectively. 
 
   
   
     2. The insulated gate bipolar transistor according to  claim 1 , further comprising
 a polysilicon layer in contact with said surface of each of said first doped regions and said main surface of said second semiconductor layer, 
 wherein said collector electrode is formed over said main surface of said second semiconductor layer to cover said surface of each of said first doped regions, with said polysilicon layer lying between said collector electrode, and said first doped regions and said second semiconductor layer. 
 
   
   
     3. The insulated gate bipolar transistor according to  claim 1 ,
 wherein said first semiconductor layer comprises a buffer layer having said first main surface, and a third semiconductor layer having said second main surface, and 
 wherein said buffer layer is formed on a main surface of said third semiconductor layer opposite from said second main surface, and has an impurity concentration higher than that of said third semiconductor layer. 
 
   
   
     4. The insulated gate bipolar transistor according to  claim 2 ,
 wherein said first semiconductor layer comprises a buffer layer having said first main surface, and a third semiconductor layer having said second main surface, and 
 wherein said buffer layer is formed on a main surface of said third semiconductor layer opposite from said second main surface, and has an impurity concentration higher than that of said third semiconductor layer. 
 
   
   
     5. The insulated gate bipolar transistor according to  claim 1 ,
 wherein said second semiconductor layer has a substantially uniform impurity concentration. 
 
   
   
     6. The insulated gate bipolar transistor according to  claim 2 ,
 wherein said second semiconductor layer has a substantially uniform impurity concentration. 
 
   
   
     7. The insulated gate bipolar transistor according to  claim 3 ,
 wherein said second semiconductor layer has a substantially uniform impurity concentration. 
 
   
   
     8. The insulated gate bipolar transistor according to  claim 4 ,
 wherein said second semiconductor layer has a substantially uniform impurity concentration.