Configurable I/Os for multi-chip modules

Abstract

An apparatus comprising an integrated circuit and a logic portion. The integrated circuit may have a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect the integrated circuit to a socket. The logic portion may be implemented on the integrated circuit. The plurality of metal programmable regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions. Each of the metal programmable regions comprises (a) a regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at the operating voltage, and (c) a level shifter configured to shift the operating voltage to an external voltage level.

1. An apparatus comprising:
 an integrated circuit having a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect said integrated circuit to a socket; and 
 a logic portion implemented on said integrated circuit, wherein said plurality of regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions, and each of said plurality of regions comprises (a) a voltage regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at said operating voltage, and (c) a level shifter configured to shift said operating voltage to an external voltage level and wherein said regions are pre-diffused during a first processing phase and configured during a second processing phase. 
 
   
   
     2. The apparatus according to  claim 1 , wherein a first of said voltage regulator sections generates a first operating voltage and a second of said voltage regulator sections generates a second operating voltage, wherein said first and second operating voltages are different. 
   
   
     3. The apparatus according to  claim 1 , wherein each of said regions further comprimises an inventor configured to drive a signal recieved from said level shifter to a strength expected by an external circuit. 
   
   
     4. The apparatus according to  claim 1 , wherein said regions are metal-programmed in different location around periphery of said intergrated circuit in response to a particular configuration of said socket. 
   
   
     5. The apparatus according to  claim 1 , wherein said first processing phase comprises a pre-inventory phase and second processing phase comprimises a completed inventory phase. 
   
   
     6. The apparatus according to  claim 1 , wherein one or more of said regions comprise built-in self test circuits. 
   
   
     7. The apparatus according to  claim 1 , wherein one or more of said regions comprise temperature compensation circuits. 
   
   
     8. The apparatus according to  claim 1 , wherein one or more of said regions comprise first order delta sigma modulator circuits. 
   
   
     9. The apparatus according to  claim 1 , wherein said integrated circuit comprises a plurality of dies configured as a multi-chip module. 
   
   
     10. The apparatus according to  claim 1 , wherein said common supply voltage is generated on a metal bus spanning each of said metal programmable regions. 
   
   
     11. The apparatus according to  claim 1 , wherein said apparatus comprises a plurality of supply voltages each generated from a metal bus, spanning each of said programmable regions. 
   
   
     12. The apparatus according to  claim 1 , wherein each of said metal programmable regions further comprises a device selected from the group consisting of transmitters, receivers and electrostatic discharge protection devices. 
   
   
     13. An apparatus comprising:
 a first integrated circuit having a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect said integrated circuit to a second integrated circuit, wherein said first and said second integrated circuits are implemented on a multi-chip module; and 
 a logic portion implemented on said integrated circuit, wherein said plurality of regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions, and each of said plurality of regions comprises (a) a regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at said operating voltage, and (c) a level shifter configured to shift said operating voltage to an external voltage level, wherein said metal programmable regions are pre-diffused during a first processing phase and configured during a second processing phase. 
 
   
   
     14. The apparatus according to  claim 13 , wherein each of said regions further comprises an inverter configured to drive a signal received from said level shifter to a strength expected by said second integrated circuit. 
   
   
     15. The apparatus according to  claim 13 , wherein said regions are metal-programmed in different locations around a periphery of said first integrated circuit in response to a particular configuration of said second integrated circuit. 
   
   
     16. The apparatus according to  claim 13 , wherein said first processing phase comprises a pre-inventory phase and said second processing phase comprises a completed-inventory phase. 
   
   
     17. The apparatus according to  claim 13 , wherein said first integrated circuit and said second integrated circuit each, comprise a plurality of dies configured as a multi-chip module. 
   
   
     18. The apparatus according to  claim 13 , wherein said apparatus comprises a plurality of supply voltages each generated from a metal bus, spanning each of said programmable regions.