Successive approximation type A/D converter

Abstract

An A/D converter of an successive approximation type according to the present invention comprises a sample hold circuit, a reference voltage generating circuit, a comparator for comparing the reference voltage generated by the reference voltage generating circuit to a value of the input analog signal retained in the sample hold circuit, a control circuit for successively controlling the reference voltage generating circuit so that a value of the reference voltage approximates to the value of the input analog signal retained in the sample hold circuit, a buffering circuit for outputting an output value corresponding to an output voltage of the comparator, a latch circuit for retaining the output value of the buffering circuit corresponding to the output value of the comparator per bit as a digital value, and a buffering control circuit for blocking a power supply to the buffering circuit during the sampling period is provided.

1. An A/D converter of an successive approximation type comprising:
 a sample hold circuit for retaining an input analog signal during a sampling period; 
 a reference voltage generating circuit for generating a reference voltage compared to the retained input analog signal during a successive comparison period; 
 a comparator for comparing the reference voltage generated by the reference voltage generating circuit to a value of the input analog signal retained in the sample hold circuit; 
 a control circuit for successively controlling the reference voltage generating circuit so that a value of the reference voltage approximates to the value of the input analog signal retained in the sample hold circuit based on an output value of the comparator per bit; 
 a buffering circuit for outputting an output value corresponding to an output voltage of the comparator; and 
 a latch circuit for retaining the output value of the buffering circuit corresponding to the output value of the comparator per bit as a digital value, wherein 
 a buffering control circuit for blocking a power supply to the buffering circuit during the sampling period is provided. 
 
   
   
     2. The A/D converter of the successive approximation type according to  claim 1 , wherein
 the buffering circuit consists of an inverter of a tri-state type, and 
 the buffering control circuit is constructed to turn off a control transistor of the tri-state inverter during the sampling period and turn on the control transistor of the tri-state inverter during the successive comparison period. 
 
   
   
     3. The A/D converter of the successive approximation type according to  claim 1 , wherein
 an inverter for buffering is further connected to a subsequent stage of the tri-state inverter constituting the buffering circuit, 
 a pull-up circuit is connected to a connection point of the tri-state inverter and the buffering inverter, and 
 the buffering control circuit is constructed to turn off a control transistor of the tri-state inverter and turn on the pull-up circuit during the sampling period, and turn on the control transistor of the tri-state inverter and turn off the pull-up circuit during the successive comparison period. 
 
   
   
     4. The A/D converter of the successive approximation type according to  claim 1 , wherein
 a first buffering circuit with a first performance and a second buffering circuit with a second performance are provided as the buffering circuit, 
 a select circuit for selecting one of the first and second buffering circuits is provided, and 
 the buffering control circuit blocks the power supply to the buffering circuit selected by the select circuit during the sampling period, while always blocking the power supply to the buffering circuit not selected by the select circuit. 
 
   
   
     5. The A/D converter of the successive approximation type according to  claim 1 , wherein
 a first comparator with a first performance and a second comparator with a second performance are provided as the comparator, and 
 a select circuit for selecting one of the first and second comparators is provided, the select circuit is always supplying the power supply to the selected comparator, while always blocking the power supply to the comparator not selected. 
 
   
   
     6. The A/D converter of the successive approximation type according to  claim 1 , wherein
 a first buffering circuit with a first performance and a second buffering circuit with a second performance are provided as the buffering circuit, 
 a first comparator with a first performance and a second comparator with a second performance are provided as the comparator, 
 a select circuit for selecting one of the first and second comparators and selecting one of the first and second buffering circuits is provided, 
 the buffering control circuit blocks the power supply to the buffering circuit selected by the select circuit during the sampling period, while always blocking the power supply to the buffering circuit not selected by the select circuit, and 
 the select circuit supplies the power supply to the selected comparator, while always blocking the power supply to the comparator not selected. 
 
   
   
     7. The A/D converter of the successive approximation type according to  claim 4 , wherein
 the select circuit is constructed to be controlled in accordance with a clock frequency. 
 
   
   
     8. The A/D converter of the successive approximation type according to  claim 5 , wherein
 the select circuit is constructed to be controlled in accordance with a clock frequency. 
 
   
   
     9. The A/D converter of the successive approximation type according to  claim 6 , wherein
 the select circuit is constructed to be controlled in accordance with a clock frequency. 
 
   
   
     10. The A/D converter of the successive approximation type according to  claim 4 , wherein
 the select circuit is constructed to be controlled in accordance with a register value externally set. 
 
   
   
     11. The A/D converter of the successive approximation type according to  claim 5 , wherein
 the select circuit is constructed to be controlled in accordance with a register value externally set. 
 
   
   
     12. The A/D converter of the successive approximation type according to  claim 6 , wherein
 the select circuit is constructed to be controlled in accordance with a register value externally set. 
 
   
   
     13. An A/D converter of an successive approximation type comprising:
 a sample hold circuit for retaining an input analog signal during a sampling period; 
 a reference voltage generating circuit for generating a reference voltage compared to the retained input analog signal during a successive comparison period; 
 a comparator for comparing the reference voltage generated by the reference voltage generating circuit to a value of the input analog signal retained in the sample hold circuit; 
 a control circuit for successively controlling the reference voltage generating circuit so that a value of the reference voltage approximates to the value of the input analog signal retained in the sample hold circuit based on an output value of the comparator per bit; 
 a buffering circuit for outputting an output value corresponding to an output voltage of the comparator; and 
 a latch circuit for retaining the output value of the buffering circuit corresponding to the output value of the comparator per bit as a digital value, wherein 
 a circuit for stopping the operation of the reference voltage generating circuit is provided in the reference voltage generating circuit so that the reference voltage generating circuit is stopped during a period when the supply of the reference voltage is unnecessary in the sampling period or a period when a voltage externally inputted is used as the reference voltage in the successive comparison period.