Thin film transistor array panel

Abstract

A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.

1. A thin film transistor array panel comprising:
 a gate line and a gate electrode formed on a substrate; 
 a gate insulating layer formed on the gate line and the gate electrode; 
 a semiconductor layer formed on the gate insulating layer, 
 a data line including a source electrode formed on the gate insulating layer; and 
 a drain electrode formed on the semiconductor layer, 
 wherein the source electrode and the drain electrode comprising a Mo alloy layer and a Cu layer, an alloying element of the Mo alloy layer forming a nitride layer as a diffusion barrier against the Cu layer. 
 
   
   
     2. The thin film transistor array panel of  claim 1 , wherein the alloying element of the Mo alloy layer is Ti, Ta, Zr or Nb. 
   
   
     3. The thin film transistor array panel of  claim 2 , wherein the content of the alloying element of the Mo alloy layer is no more than 10 atm %. 
   
   
     4. The thin film transistor array panel of  claim 1 , wherein the content of nitrogen in the nitride layer is from 0.01 atm % to 50 atm %. 
   
   
     5. The thin film transistor array panel of  claim 1 , wherein the nitride layer is formed between the Mo alloy layer and the Cu layer. 
   
   
     6. The thin film transistor array panel of  claim 1 , wherein the nitride layer is formed between the Mo alloy layer and the semiconductor layer. 
   
   
     7. The thin film transistor array panel of  claim 1 , wherein the nitride layer is formed between the Mo alloy layer and the Cu layer, and a second nitrogen layer is formed between the Mo alloy layer and the semiconductor layer. 
   
   
     8. The thin film transistor array panel of  claim 1 , wherein the nitride layer formed in the Mo alloy layer. 
   
   
     9. The thin film transistor array panel of  claim 1 , wherein the thickness of the nitride layer is more than 5 Angstroms. 
   
   
     10. The thin film transistor array panel of  claim 1 , further comprising a pixel electrode connected to the drain electrode.