Sigma-delta modulator for PLL circuits

Abstract

A sigma-delta modulator for generating a modulation signal that modulates a frequency division ratio of a comparator/frequency divider of a PLL circuit. Series-connected integrators accumulate an input signal and output overflow signals when their accumulated values exceed a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies output signals output from the differentiators by a predetermined coefficient and adds the products. A control circuit for transferring the accumulated value in synchronization with a clock signal of each integrator is connected between the integrator of a final stage and the integrator of the preceding stage. The control circuit reduces the modulation width of the modulation signal without reducing the order number of the modulator.

1. A sigma-delta modulator for generating a modulation signal for modulating a frequency division ratio for a comparator/frequency divider of a PLL circuit, the sigma-delta modulator comprising:
 a plurality of series-connected integrators, each accumulating an input signal based on a clock signal and outputting an overflow signal when an accumulated value exceeds a predetermined value; 
 a plurality of differentiators selectively connected to the plurality of integrators, each of the differentiators transferring an overflow signal of a corresponding one of the integrators; 
 an adder for multiplying the overflow signals transferred from the plurality of differentiators by a predetermined coefficient and adding the products to generate the modulation signal; and 
 a control circuit, connected between a first integrator of a final stage and a second integrator of a stage preceding the final stage, for providing an output signal of the second integrator to the first integrator in synchronization with a frequency-divided signal obtained by frequency-dividing the clock signal. 
 
     
     
       2. The sigma-delta modulator according to  claim 1 , wherein the control circuit includes:
 a frequency-dividing circuit for dividing the frequency of the clock signal to generate the frequency-divided signal; and 
 a gate circuit, connected between the second integrator and the first integrator, for outputting an accumulated value of the second integrator to the first integrator in synchronization with the frequency-divided signal generated by the frequency-dividing circuit. 
 
     
     
       3. The sigma-delta modulator according to  claim 1 , wherein the control circuit includes:
 a setting unit for generating a frequency division ratio setting signal for setting the frequency division ratio to frequency-divide the clock signal; 
 a frequency-dividing circuit for frequency-dividing the clock signal based on the frequency division ratio setting signal to generate the frequency-divided signal; and 
 a gate circuit, connected between the second integrator and the first integrator, for providing an accumulated value of the second integrator to the first integrator in synchronization with the frequency-divided signal of the frequency-dividing circuit. 
 
     
     
       4. The sigma-delta modulator according to  claim 3 , wherein the setting unit enables the frequency division ratio setting signal to be adjusted based on data input from an external device. 
     
     
       5. The sigma-delta modulator according to  claim 3 , wherein the setting unit includes a shift register for generating the frequency division ratio setting signal, which has a plurality of bits, based on data input from an external device. 
     
     
       6. The sigma-delta modulator according to  claim 2 , wherein the frequency-dividing circuit includes a binary counter formed by a plurality of series-connected flip-flop circuits. 
     
     
       7. The sigma-delta modulator according to  claim 3 , wherein the frequency-dividing circuit includes:
 a binary counter including a plurality of series-connected flip-flop circuits, each generating an output signal in accordance with the frequency division ratio setting signal; and 
 a logic circuit unit for synthesizing the output signals of the flip-flop circuits to generate the frequency-divided signal. 
 
     
     
       8. The sigma-delta modulator according to  claim 7 , wherein the frequency-dividing circuit enables the frequency division ratio to be selected from any one of 1 to  2   n −1 by selecting the output signal of a flip-flop circuit in the nth stages that is output to the logic circuit unit in accordance with the frequency division ratio setting signal. 
     
     
       9. The sigma-delta modulator according to  claim 2 , wherein the gate circuit includes a plurality of AND circuits, each receiving the frequency-divided signal and a corresponding one of a plurality of bits in the output signal of the second integrator. 
     
     
       10. A PLL circuit comprising:
 a sigma-delta modulator for generating a modulation signal for modulating a frequency division ratio for a comparator/frequency divider of a PLL circuit, the sigma-delta modulator including:
 a plurality of series-connected integrators, each accumulating an input signal based on a clock signal and outputting an overflow signal when an accumulated value exceeds a predetermined value; 
 a plurality of differentiators selectively connected to the plurality of integrators, each of the differentiators transferring an overflow signal of a corresponding one of the integrators; 
 an adder for multiplying the overflow signals transferred from the plurality of differentiators by a predetermined coefficient and adding the products to generate the modulation signal; and 
 a control circuit, connected between a first integrator of a final stage and a second integrator of a stage preceding the final stage, for providing an output signal of the second integrator to the first integrator in synchronization with a frequency-divided signal obtained by frequency-dividing the clock signal; and 
 
 a comparator/frequency divider, connected to the sigma-delta modulator, for performing a fractional frequency division operation according to a modulation signal of the sigma-delta modulator. 
 
     
     
       11. A fractional-N PLL frequency synthesizer, comprising:
 a sigma-delta modulator for generating a modulation signal for modulating a frequency division ratio for a comparator/frequency divider of a PLL circuit, the sigma-delta modulator including:
 a plurality of series-connected integrators, each accumulating an input signal based on a clock signal and outputting an overflow signal when an accumulated value exceeds a predetermined value; 
 a plurality of differentiators selectively connected to the plurality of integrators, each of the differentiators transferring an overflow signal of a corresponding one of the integrators; 
 an adder for multiplying the overflow signals transferred from the plurality of differentiators by a predetermined coefficient and adding the products to generate the modulation signal; and 
 a control circuit, connected between a first integrator of a final stage and a second integrator of a stage preceding the final stage, for providing an output signal of the second integrator to the first integrator in synchronization with a frequency-divided signal obtained by frequency-dividing the clock signal; 
 
 a comparator/frequency divider, connected to the sigma-delta modulator, for performing a fractional frequency division operation in accordance with a modulation signal of the sigma-delta modulator and generating a comparison signal; 
 a reference frequency divider for generating a reference signal; and 
 a phase comparator, connected to the comparator/frequency divider and the reference frequency divider, for comparing the reference signal and the comparison signal and generating a phase comparison signal.