Systems and methods for variable control of power dissipation in a pipelined processor

Abstract

The invention controls maximum average power dissipation by stalling high power instructions through the pipeline of a pipelined processor. A power dissipation controller stalls the high power instructions in order to control the processor's maximum average power dissipation. Preferably, the controller is modeled after a capacitive system with a constant output rate and a throttled input rate: the output rate represents the steady state maximum average power dissipation; while the input rate is stalled based upon current capacity, representing thermal response time. At start-up, the capacity is initialized. Yet for each high power instruction, the capacity increases by a weighted value. Each clock capacity is also decreased by a variable output rate. In particular, a low power operation is inserted to the stage execution circuit where the stall is desired, creating a low power state for that circuit. This stall effectively creates a “hole” at that pipeline stage, thus temporarily reducing power dissipation. The invention takes advantage of the fact that the presence of an instruction at any stage execution circuit dissipates power and that the absence (i.e., a “hole”) of an instruction at any stage dissipates less power. By controlling where and when a hole occurs within the pipeline, the maximum average power dissipation of the processor is controlled.

1. A computing system, comprising:
 a plurality of pipelined processors, each processor having a power dissipation controller for variably controlling internally generated power dissipation to a capacitive model which achieves substantially maximum average power output dissipation relative to throttled instruction input rate; and 
 a cooler for cooling the system relative to power dissipated from the processors. 
 
   
   
     2. A system of  claim 1 , further comprising operating system software for specifying constants within register memory within the controller, the constants forming the capacitive model. 
   
   
     3. A system of  claim 1 , wherein the controller inserts a lp-bit to one or more stage execution circuits within the processor in order to stall high powered instructions through a pipeline. 
   
   
     4. A system of  claim 1 , wherein each processor further comprises at least one additional power dissipation controller for controlling processing in different pipelines. 
   
   
     5. A pipelined processor of the type having at least one register pipeline, comprising:
 a power dissipation controller for stalling instructions to control average power dissipation of the pipelined processor; 
 logic for comparing a threshold to current capacity representative of a thermal response of the pipelined processor and for implementing a lower power state within the register pipeline of the pipelined processor when the capacity exceeds the threshold; and 
 register memory for storing constants of capacitive feedback. 
 
   
   
     6. The pipelined processor of  claim 5 , the constants being written to the register memory and including a bleed rate, one or more issue weights, and the threshold. 
   
   
     7. The pipelined processor of  claim 6 , the logic computing current capacity as a number of issued instructions multiplied by the issue weights and subtracted by the bleed rate. 
   
   
     8. The pipelined processor of  claim 7 , the issue weights corresponding to relative power dissipation, wherein issue weights for higher power instructions are greater than issue weights for lower power instructions. 
   
   
     9. The pipelined processor of  claim 5 , the power dissipation controller inserting a low power operation to the register pipeline to stall the instructions. 
   
   
     10. A power dissipation controller for controlling power dissipation within a pipelined processor, comprising:
 a register access bus for setting a bleed rate; 
 logic for multiplying each instruction of the pipelined processor by an issue weight; and 
 logic for stalling instructions of the pipelined processor when capacity of the pipelined processor exceeds a threshold, wherein the capacity is determined as being (a) reduced by the bleed rate and (b) increased by the instruction multiplied by the issue weight.