Method and apparatus for automatic frequency correction with a frequency error signal generated by block correlation of baseband samples with a known code sequence

Abstract

The present invention is related to a method and apparatus for automatic frequency correction of a local oscillator. The apparatus receives a carrier signal. The carrier signal includes a code sequence known to the apparatus. The apparatus downconverts the carrier signal to a baseband signal using the local oscillator. The apparatus performs a block correlation of the samples of the baseband signal with the known code sequence to generate a frequency error signal. The frequency error signal is fed back to the local oscillator to correct the frequency error.

1. A method for automatically correcting a frequency error of a local oscillator in a receiver, the method comprising:
 receiving a carrier signal, the carrier signal including a code sequence known to the receiver; 
 down-converting the carrier signal to a baseband signal; 
 sampling the baseband signal to generate samples; 
 performing a correlation of the samples and the code sequence with a plurality of block correlators to generate a plurality of correlation values, each of the block correlators performing a correlation of a portion of the samples and a corresponding portion of the code sequence; 
 generating a conjugate product and sum of the plurality of correlation values by multiplying correlation values generated by consecutive block correlators in a conjugate sense to generate a plurality of conjugate products and summing the conjugate products; 
 computing an angle value of the conjugate product and sum; 
 computing a frequency error estimate by multiplying a constant to the angle value; 
 generating a correction signal based on the frequency error estimate; and 
 feeding the correction signal to the local oscillator to correct the frequency error. 
 
     
     
       2. The method of  claim 1  further comprising:
 accumulating the conjugate product and sum over N code sequences, whereby the angle value is generated from the accumulated conjugate product and sum. 
 
     
     
       3. The method of  claim 2  wherein the number N is adjusted in accordance with the frequency error estimate. 
     
     
       4. The method of  claim 1  further comprising:
 performing a plurality of correlations of the samples and the code sequence at each of a plurality of lags to generate a plurality of correlation values at each of the lags; 
 computing a plurality of conjugate product and sums of the correlation values at the lags; 
 combining the conjugate product and sums; and 
 computing the angle value from the combined conjugate product and sums. 
 
     
     
       5. The method of  claim 4  further comprising:
 computing a magnitude of each of the conjugate product and sums; and 
 selecting a predetermined number of largest conjugate product and sums, whereby only the selected largest conjugate product and sums are combined. 
 
     
     
       6. The method of  claim 5  further comprising:
 comparing each of the selected conjugate product and sums with a threshold; and 
 removing a conjugate product and sum which is less than the threshold. 
 
     
     
       7. The method of  claim 6  wherein the threshold is determined based on a peak magnitude among the selected conjugate product and sums. 
     
     
       8. The method of  claim 1  wherein the baseband signal is sampled at twice the chip rate. 
     
     
       9. The method of  claim 1  wherein the angle value is computed using an approximation method. 
     
     
       10. The method of  claim 1  wherein the code sequence is a midamble code. 
     
     
       11. The method of  claim 10  wherein the midamble code is detected in a primary common control physical channel. 
     
     
       12. The method of  claim 11  wherein midamble codes contained in a DCH are further utilized in calculating the angle value. 
     
     
       13. The method of  claim 1  wherein multiple code sequences are simultaneous transmitted via the carrier signal, whereby the frequency error estimate is computed using the multiple code sequences. 
     
     
       14. The method of  claim 1  further comprising:
 comparing the frequency error signal with a threshold; and 
 generating a convergence indication signal when the frequency error signal is less than the threshold. 
 
     
     
       15. An automatic frequency correction (AFC) processor for automatically correcting a frequency error of a local oscillator in a receiver, the AFC unit comprising:
 a bank of block correlators configured to perform a correlation of samples of received signal and a code sequence which is known to the receiver to generate a plurality of correlation values, each of the block correlators performing a correlation of a portion of the samples and a corresponding portion of the code sequence; 
 a conjugate product and sum unit configured to generate a conjugate product and sum of the plurality of correlation values by multiplying correlation values generated by consecutive block correlators in a conjugate sense to generate a plurality of conjugate products and summing the conjugate products; and 
 an angle extraction unit configured to compute an angle value of the conjugate product and sum and a frequency error estimate by multiplying a constant to the angle value, and generate a correction signal based on the frequency error estimate, whereby the correction signal is fed to the local oscillator to correct the frequency error. 
 
     
     
       16. The AFC processor of  claim 15  further comprising:
 an accumulator for accumulating the conjugate product and sum over N code sequences, whereby the angle extraction unit computes the angle value from the accumulated conjugate product and sum. 
 
     
     
       17. The AFC processor of  claim 16  wherein the number N is adjusted in accordance with the frequency error estimate. 
     
     
       18. The AFC processor of  claim 16  further comprising:
 a plurality of bank of block correlators for performing a plurality of correlations of the samples and the code sequence at each of a plurality of lags to generate a plurality of correlation values at each of the lags; 
 a plurality of conjugate product and sum units for computing a plurality of conjugate product and sums of the correlation values at the lags; and 
 a combiner for combining the conjugate product and sums, whereby the angle extraction unit computes the angle value from the combined conjugate product and sums. 
 
     
     
       19. The AFC processor of  claim 18  further comprising:
 a magnitude calculator for computing a magnitude of each of the conjugate product and sums; and 
 a selection unit for selecting a predetermined number of largest conjugate product and sums, whereby only the selected largest conjugate product and sums are combined. 
 
     
     
       20. The AFC processor of  claim 19  further comprising:
 a threshold unit for comparing each of the selected conjugate product and sums with a threshold and removing a conjugate product and sum which is less than the threshold. 
 
     
     
       21. The AFC processor of  claim 20  wherein the threshold unit determines the threshold a peak magnitude among the selected conjugate product and sums. 
     
     
       22. The AFC processor of  claim 15  wherein the angle extraction unit computes the angle value using an approximation method. 
     
     
       23. The AFC processor of  claim 15  wherein the code sequence is a midamble code. 
     
     
       24. The AFC processor of  claim 23  wherein the midamble code is detected in a primary common control physical channel (P-CCPCH). 
     
     
       25. The AFC processor of  claim 24  wherein midamble codes contained in a DCH are further utilized in calculating the angle value. 
     
     
       26. The AFC processor of  claim 15  wherein multiple code sequences are simultaneous transmitted via the carrier signal, whereby the frequency error estimate is computed using the multiple code sequences. 
     
     
       27. The AFC processor of  claim 15  further comprising:
 a comparator for comparing the frequency error signal with a threshold and generating a convergence indication signal when the frequency error signal is less than the threshold.