Liquid crystal display device having driving circuit and method of fabricating the same

Abstract

A polycrystalline silicon thin film transistor of a bottom gate structure is used as a switching element and a mask having transmissive, half-transmissive and blocking areas is used so that an array substrate for a liquid crystal display device having a monolithic driving circuit can be fabricated through a six-mask process.

1. A method of fabricating an array substrate structure for a liquid crystal display device, comprising:
 sequentially forming a transparent conductive material layer and a metallic material layer on a substrate defining a display area and a non-display area, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion; 
 forming a first gate electrode in the p-type driving TFT portion, a second gate electrode in the n-type driving TFT portion, a third gate electrode in the pixel TFT portion, a gate line in the display area, a pixel electrode in the pixel electrode area, and a first capacitor electrode connected to the pixel electrode through a first mask process; 
 sequentially forming a gate insulating layer and a silicon layer on the first gate electrode, the second gate electrode, the third gate electrode, the gate line, the pixel electrode and the first capacitor electrode; 
 doping the silicon layer in the p-type driving TFT portion with high concentration p-type impurities (p+) through a second mask process to define a first active region and a first ohmic contact region; 
 doping the silicon layer in the pixel TFT portion and the n-type driving TFT portion with high concentration n-type impurities (n+) and low concentration n-type impurities (n−) through a third mask process to define second and third active regions, second and third ohmic contact regions, first and second lightly doped drain (LDD) regions and a storage capacitor area; 
 forming a first semiconductor layer in the p-type driving TFT portion, a second semiconductor layer in the n-type driving TFT portion, a third semiconductor layer in the pixel TFT portion, and a second capacitor electrode in the storage capacitor area through a fourth mask process; 
 forming a passivation pattern on the first, second and third semiconductor layers through a fifth mask process, wherein the passivation pattern covers the first, second and third active regions, and wherein the first, second and third ohmic contact regions are exposed through the passivation pattern; and 
 forming first source and drain electrodes, second source and drain electrodes, third source and drain electrodes and a data line through a sixth mask process, the first source and drain electrodes contacting the first ohmic contact region, the second source and drain electrodes contacting the second ohmic contact region, the third source and drain electrodes contacting the third ohmic contact region, and the data line connected to the third source electrode. 
 
     
     
       2. The method according to  claim 1 , further comprising crystallizing the silicon layer. 
     
     
       3. The method according to  claim 1 , wherein the gate insulating layer includes an inorganic insulating material. 
     
     
       4. The method according to  claim 1 , wherein the passivation layer includes an inorganic insulating material. 
     
     
       5. The method according to  claim 1 , wherein the first semiconductor layer includes the first active region, the first ohmic contact region, wherein the second semiconductor layer includes the second active region, the second ohmic contact region and the first LDD region, wherein the third semiconductor layer includes the third active region and the third ohmic contact region and the second LDD region. 
     
     
       6. The method according to  claim 1 , wherein the first mask process comprises:
 forming a photoresist (PR) layer on the metallic material layer; 
 disposing a gate-pixel mask having a transmissive area, a blocking area and a half-transmissive area over the PR layer, a light transmittance of the half-transmissive is lower than that of the transmissive area and higher than that of the blocking area; 
 exposing the PR layer through the gate-pixel mask; 
 developing the PR layer to form a first gate-pixel PR pattern having a first thickness and a second gate-pixel PR pattern having a second thickness greater than the first thickness, the first gate-pixel PR pattern overlapping the first, second, and third gate electrodes, the pixel electrode, and the first capacitor electrode, and the second gate-pixel PR pattern overlapping the gate line; 
 sequentially etching the metallic material layer and the transparent conductive material layer using the first and second gate-pixel PR patterns as an etching mask; 
 removing the first gate-pixel PR pattern to expose the metallic material layer; 
 etching the metallic material layer to expose the transparent conductive material layer; and 
 removing the second gate-pixel PR pattern. 
 
     
     
       7. The method according to  claim 6 , wherein the PR layer has a positive type, the half-transmissive area corresponds to the first gate-pixel PR pattern and the blocking area corresponds to the second gate-pixel PR pattern. 
     
     
       8. The method according to  claim 6 , wherein removing the first gate-pixel PR pattern comprises removing a portion of the second gate-pixel PR pattern to reduce the second thickness. 
     
     
       9. The method according to  claim 8 , wherein removing the first gate-pixel PR pattern and partially removing the second gate-pixel PR pattern are performed anisotropically by at least one of ashing and stripping methods. 
     
     
       10. The method according to  claim 1 , wherein the gate line includes a double layer of the transparent conductive material layer and the metallic material layer. 
     
     
       11. The method according to  claim 1 , wherein the gate electrode includes a single layer of the transparent conductive material layer. 
     
     
       12. The method according to  claim 1 , further comprising disposing a buffer layer between the substrate and the transparent conductive material layer. 
     
     
       13. The method according to  claim 12 , wherein the buffer layer includes at least one of silicon nitride (SiNx) and silicon oxide (SiO 2 ). 
     
     
       14. The method according to  claim 1 , wherein the transparent conductive material layer includes at least one of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). 
     
     
       15. The method according to  claim 1 , wherein the transparent conductive material layer has a thickness within a range of about 500 Å to about 1000 Å. 
     
     
       16. The method according to  claim 1 , wherein the metallic material layer includes molybdenum (Mo). 
     
     
       17. The method according to  claim 1 , wherein the metallic material layer has a thickness less than about 3000 Å. 
     
     
       18. The method according to  claim 1 , wherein the second mask process comprises:
 forming a p+ PR pattern on the silicon layer, the p+ PR pattern exposing a portion of the silicon layer corresponding to the first ohmic contact region; 
 doping the exposed silicon layer with the high concentration p-type impurities using the p+ PR pattern as a doping mask; and 
 removing the p+ PR pattern. 
 
     
     
       19. The method according to  claim 18 , wherein the high concentration p-type impurities has a dose within a range of about 1×10 15  cm −2  to about 9×10 16  cm −2 . 
     
     
       20. The method according to  claim 1 , wherein the third mask process comprises:
 forming an n+ PR pattern on the silicon layer, the n+ PR pattern exposing first portions of the silicon layer corresponding to the second and third ohmic contact regions; 
 doping the exposed silicon layer with the high concentration n-type impurities using the n+ PR pattern as a doping mask; 
 removing portions of the n+ PR pattern to form an n− PR pattern exposing a second portions of the polycrystalline silicon layer corresponding to the first and second LDD regions; 
 doping the polycrystalline silicon layer in the first and second LDD regions with the low concentration n-type impurities using the n− PR pattern as a doping mask; and 
 removing the n− PR pattern. 
 
     
     
       21. The method according to  claim 20 , wherein the high concentration n-type impurities has a dose within a range of about 1×10 15  cm −2  to about 9×10 16  cm −2 , and the low concentration n-type impurities has a dose within a range of about 1×10 13  cm −2  to about 9×10 13  cm −2 . 
     
     
       22. The method according to  claim 1 , wherein the third drain electrode directly contacts the pixel electrode. 
     
     
       23. The method according to  claim 1 , wherein the passivation layer covers the gate line and the second capacitor electrode. 
     
     
       24. The method according to  claim 1 , wherein the passivation layer has a contact hole exposing the pixel electrode and the third drain electrode is connected to the pixel electrode through the contact hole. 
     
     
       25. A method of fabricating an array substrate structure for a liquid crystal display device, comprising:
 sequentially disposing a transparent conductive material layer and a metallic material layer on a substrate defining a display area and a non-display area, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having a driving TFT portion; 
 forming a first gate electrode in the pixel TFT portion and a second gate electrode in the driving TFT portion, a gate line in the display area, a pixel electrode in the pixel electrode area through a first mask process, wherein a first capacitor electrode is connected to the pixel electrode; 
 sequentially disposing a gate insulating layer and a silicon layer on the first, second gate electrodes, the gate line, the pixel electrode, and the first capacitor electrode; 
 doping the silicon layer with impurities through a second mask process to define a first active region, a first ohmic contact region, and storage capacitor area in the pixel TFT portion, and a second active region and a second ohmic contact region in the driving TFT portion; 
 forming a first semiconductor layer in the pixel TFT portion, a second semiconductor layer in the driving TFT portion, and a second capacitor electrode in the storage capacitor area through a third mask process; 
 forming a passivation pattern on the first and second silicon layer through a fourth mask process, wherein the passivation pattern covers the first and second active regions, and wherein the first and second ohmic contact regions are exposed through the passivation pattern; 
 forming first source and drain electrodes, second source and drain electrodes, and a data line through a fifth mask process, the first source and drain electrodes contacting the first ohmic contact region, the second source and drain electrodes contacting the second ohmic contact region, and the data line connected to the first source electrode. 
 
     
     
       26. The method according to  claim 25 , wherein the impurities include at least one of n-type and p-type impurities. 
     
     
       27. The method according to  claim 25 , further comprising crystallizing the silicon layer. 
     
     
       28. The method according to  claim 25 , wherein the first mask process comprises:
 disposing a PR layer on the metallic material layer; 
 disposing a gate-pixel mask having a transmissive area, a blocking area and a half-transmissive area over the PR layer, a light transmittance of the half-transmissive area is lower than that of the transmissive area and higher than that of the blocking area; 
 exposing the PR layer using the gate-pixel mask; 
 developing the PR layer to form a first gate-pixel PR pattern having a first thickness and a second gate-pixel PR pattern having a second thickness greater than the first thickness, the first gate-pixel PR pattern overlapping the first and second gate electrodes, the pixel electrode, and the first capacitor electrode, the second gate-pixel PR pattern overlapping the gate line; 
 sequentially etching the metallic material layer and the transparent conductive material layer using the first and second gate-pixel PR patterns as an etching mask; 
 removing the first gate-pixel PR pattern to expose the metallic material layer; etching the metallic material layer to expose the transparent conductive material layer; and 
 removing the second gate-pixel PR pattern. 
 
     
     
       29. The method according to  claim 25 , wherein the second mask process comprises:
 forming a doping PR pattern on the polycrystalline silicon layer, the doping PR pattern exposing a portion of the polycrystalline silicon layer corresponding to the first and second ohmic contact regions; 
 doping the polycrystalline silicon layer with the impurities using the doping PR pattern as a doping mask; and 
 removing the doping pattern.