High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion

Abstract

Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.

1. A translator for translating differential input signals into a CMOS logic output, comprising:
 a level-shifting and buffering stage configured to receive the differential input signals and to provide a set of level shifted signals; 
 a gain stage configured to receive the set of level shifted signals and to provide a set of increased swing signals; and 
 a CMOS buffer configured to receive the set of increased swing signals and to provide the CMOS logic output, 
 wherein the level shifting and buffering stage includes a first buffer receiving the differential input signals and a second buffer, said second buffer coupled with the first buffer,
 the first buffer being a first passively-loaded differential structure including:
 a first transistor receiving a first input signal of said differential input signals; 
 a second transistor receiving a second input signal of said differential input signals, the first transistor and the second transistor connected in parallel at a node; and 
 a third transistor connected between the node and ground; 
 
 the first buffer providing a set of intermediate level shifted signals; 
 the second buffer being a second passively-loaded differential structure configured to receive the set of intermediate level shifted signals and to provide the set of level shifted signals. 
 
 
   
   
     2. A translator for translating differential input signals into a CMOS logic output, comprising:
 a level-shifting and buffering stage configured to receive the differential input signals and to provide a set of level shifted signals; 
 a gain stage configured to receive the set of level shifted signals and to provide a set of increased swing signals; and 
 a CMOS buffer configured to receive the set of increased swing signals and to provide the CMOS logic output, 
 wherein the level shifting and buffering stage includes a first buffer receiving the differential input signals and a second buffer, said second buffer coupled with the first buffer,
 the first buffer being a first passively-loaded differential structure including:
 a first transistor receiving a first input signal of said differential input signals; 
 a second transistor receiving a second input signal of said differential input signals, the first transistor and the second transistor connected in parallel at a node; and 
 a third transistor connected between the node and ground; 
 
 the first buffer providing a set of intermediate level shifted signals; 
 the second buffer being a second passively-loaded differential structure configured to receive the set of intermediate level shifted signals and to provide the set of level shifted signals, 
 wherein the first and second transistors are n-channel transistors. 
 
 
   
   
     3. A translator for translating differential input signals into a CMOS logic output, comprising:
 a level-shifting and buffering stage configured to receive the differential input signals and to provide a set of level shifted signals; 
 a gain stage configured to receive the set of level shifted signals and to provide a set of increased swing signals; and 
 a CMOS buffer configured to receive the set of increased swing signals and to provide the CMOS logic output, 
 wherein the level shifting and buffering stage includes a first buffer receiving the differential input signals and a second buffer, said second buffer coupled with the first buffer,
 the first buffer being a first passively-loaded differential structure including:
 a first transistor receiving a first input signal of said differential input signals; 
 a second transistor receiving a second input signal of said differential input signals, the first transistor and the second transistor connected in parallel at a node; and 
 a third transistor connected between the node and ground; 
 
 the first buffer providing a set of intermediate level shifted signals; 
 the second buffer being a second passively-loaded differential structure configured to receive the set of intermediate level shifted signals and to provide the set of level shifted signals, 
 wherein the first buffer includes at least one pull-up resistor, and 
 wherein the first and second transistors are coupled with the at least one pull-up resistors.