Method for fabricating doped polysilicon lines

Abstract

A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

1. A method of fabricating a semiconductor structure, comprising:
 (a) providing a substrate; 
 (b) forming a dielectric layer on a top surface of said substrate; 
 (c) forming a polysilicon layer on a top surface of said dielectric layer; 
 (d) implanting a less than whole first portion of said polysilicon layer with N-dopant species, said N-dopant species about contained within said polysilicon layer; 
 (e) implanting a less than whole second portion of said polysilicon layer with P-dopant species, said second portion different from said first portion, said P-dopant species about contained within said polysilicon layer; 
 (f) implanting said first portion of said polysilicon layer with a first nitrogen containing species, said first nitrogen containing species essentially contained within said polysilicon layer; and 
 after (a), (b), (c), (d), (e) and (f), (g) patterning said first portion of said polysilicon layer into a first polysilicon line and patterning said second portion of said polysilicon layer into a second polysilicon line. 
 
   
   
     2. The method of  claim 1 , further including:
 prior to (g), implanting said second portion of said polysilicon layer with a second nitrogen containing species. 
 
   
   
     3. The method of  claim 1 , wherein a peak concentration of said N-dopant species is about equal to a peak concentration of said first nitrogen containing species at about a same distance from a top surface of said polysilicon layer. 
   
   
     4. The method of  claim 1 , wherein a surface concentration of said N-dopant species is about equal to a surface concentration of said first nitrogen containing species at about a same distance from a top surface of said polysilicon layer. 
   
   
     5. The method of  claim 1 , wherein said N-dopant species and said first nitrogen containing species have about a same ion implantation concentration profile. 
   
   
     6. The method of  claim 1 , wherein a surface concentration of said N-dopant species is between about 1E18 atm/cm 3  to about 1E22 atm/cm 3  and a surface concentration of said first nitrogen containing species is between about 1E18 atm/cm 3  to about 1E21 atm/cm 3 . 
   
   
     7. The method of  claim 1 , wherein:
 wherein a peak concentration of said N-dopant species is between about 1E18 atm/cm 3  to about 1E22 atm/cm 3  and a peak concentration of said first nitrogen containing species is between about 1E18 atm/cm 3  to about 1E21 atm/cm 3 ; and 
 said peak concentration of said N-dopant species occurring between a distance of about 0 nm and about ⅓ of a thickness of said polysilicon layer from a top surface of said polysilicon layer and said peak concentration of said nitrogen containing species occurring between about 0 nm to about ⅔ of said thickness of said polysilicon layer from said top surface of said polysilicon layer. 
 
   
   
     8. The method of  claim 1 , wherein:
 said N-dopant species is selected from the group consisting of phosphorus and arsenic; and 
 said first nitrogen containing species is selected from the group consisting of N, N 2 , NO, NF 3 , N 2 O and NH 3 . 
 
   
   
     9. The method of  claim 1 , further including:
 before (b), forming an N-well and a P-well in said substrate, wherein at least a portion of said first polysilicon line is formed over said P-well formed in said substrate and at least a portion of said second polysilicon line is formed over said N-well formed in said substrate, wherein an NFET gate electrode comprises a portion of said first polysilicon line and wherein a PFET gate electrode comprises a portion of said second polysilicon line; and 
 after (g), (h) performing a thermal oxidation of sidewalls and top surfaces of said NFET and PFET gate electrodes to form a thermal oxide layer on sidewalls of said NFET and PFET gate electrodes. 
 
   
   
     10. The method of  claim 9 , wherein said nitrogen containing species retards oxidation of said NFET gate electrode. 
   
   
     11. The method of  claim 9 , further including:
 after (g), (i) implanting regions of said P-well on opposite sides of said NFET gate electrode with an N-type dopant species to form a source and a drain in said P-well and implanting regions of said N-well on opposite sides of said PFET gate electrode with a P-type dopant species to form a source and a drain in said N-well. 
 
   
   
     12. The method of  claim 11 , further including:
 after (i), forming respective metal silicide layers on said surfaces of said NFET and PFET gate electrodes and said sources and drains in said N-well and said P-well. 
 
   
   
     13. The method of  claim 9 , further including,
 before forming said P-well and N-well, forming a dielectric trench isolation in said substrate, said dielectric trench isolation extending from said top surface of said substrate into said substrate, said P-well and said N-well abutting opposite sidewalls of said trench isolation. 
 
   
   
     14. The method of  claim 1 , further including:
 forming a dielectric trench isolation in said substrate, said dielectric trench isolation extending from said top surface of said substrate into said substrate. 
 
   
   
     15. The method of  claim 14 , wherein (d) includes forming a first ion implantation masking layer on a top surface of said polysilicon layer, said first ion implantation masking layer overlapping said trench dielectric layer, covering said second portion of said polysilicon layer and preventing implantation of said N-dopant species into said second portion of said polysilicon layer, and wherein (e) includes forming a second ion implantation masking layer on a top surface of said polysilicon layer, said second ion implantation masking layer overlapping said trench dielectric layer, covering said first portion of said polysilicon layer and preventing implantation of said P-dopant species into said first portion of said polysilicon layer. 
   
   
     16. The method of  claim 15 , wherein (e) includes forming a third ion implantation masking layer on a top surface of said polysilicon layer, said third ion implantation masking layer overlapping said trench dielectric layer, covering said second portion of said polysilicon layer and preventing implantation of said nitrogen containing species into said second portion of said polysilicon layer. 
   
   
     17. The method of  claim 14 , wherein (e) includes forming an ion implantation masking layer on a top surface of said polysilicon layer, said ion implantation masking overlapping said trench dielectric layer, covering said second portion of said polysilicon layer and preventing implantation of said nitrogen containing species into said second portion of said polysilicon layer. 
   
   
     18. The method of  claim 2 , wherein said first and second nitrogen containing species are the same species. 
   
   
     19. The method of  claim 2 , wherein said first and second nitrogen containing species are the same species and (f) and (h) are performed simultaneously.