Etching method in a semiconductor processing and etching system for performing the same

Abstract

Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

1. An etching method in a semiconductor process, comprising:
 generating plasma in a plasma chamber while setting a bias power applied to a wafer in the plasma chamber to zero and applying a source power; 
 applying the generated plasma to an inner wall of the plasma chamber for a predetermined time while setting the bias power to zero for removing residual by-products on the inner wall of the plasma chamber; and 
 implementing an etching process onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value, 
 wherein conditions of pressure, temperature and gas atmosphere during setting the bias power to zero and generating the source power are set to same conditions as in the etching process. 
 
     
     
       2. An etching method as claimed in  claim 1 , wherein the predetermined time is in a range of from about 5 seconds to about 90 seconds. 
     
     
       3. An etching method as claimed in  claim 1 , wherein different regions of the wafer having different pattern densities are formed after completing the etching process. 
     
     
       4. An etching method as claimed in  claim 1 , wherein a gate pattern is formed after completing the etching process. 
     
     
       5. An etching method as claimed in  claim 4 , wherein the gate pattern is comprised of a WSi layer and a polysilicon layer, and a respective etching gas for implementing the etching process is Cl 2 /SF 6  and HBr/O 2 . 
     
     
       6. An etching method as claimed in  claim 1 , wherein the step of generating plasma while setting a bias power applied to a wafer to zero and applying a source power and the step of implementing an etching process by setting the bias power to a predetermined value are executed in-situ.