Intrinsic decoupling capacitor

Abstract

A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and the underlying epitaxial silicon layer. A larger interface area between N-doped and P-doped regions generally increases the capacitance. By providing the N-doped strip portions, as opposed to a continuous N-doped region, the combined interface area between the N-doped strip portions and the underlying epitaxial silicon layer is reduced. However, more interface area is provided between the N-doped strip portions and the P-doped strip portions. A circuit simulation indicates that junction capacitance per unit peripheral length is 0.41 fF/μm, while the junction capacitance per unit area is 0.19 fF/μm^2. Junction capacitance per unit peripheral length thus scales faster than junction capacitance per unit area.

1. A semiconductor structure, comprising:
 at least one P-doped region; 
 an N-well having at least two opposing portions with sides adjacent opposing sides of the P-doped region, and a linking section connecting the opposing portions to one another; 
 an N-well tap in the N-well, having a higher N-type conductivity concentration than the N-well; 
 a first conductive contact formed on the N-well tap; and 
 a first conductor connected to the first conductive contact to provide a voltage potential to the N-well region and a capacitance between the N-doped portions and the P-doped region. 
 
   
   
     2. The semiconductor structure of  claim 1 , further comprising a P-doped epitaxial layer, a P-well, the P-doped region being connected through the P-doped epitaxial layer to the P-well, a P-well tap in the P-well having a higher P-type conductivity concentration than the P-well, a conductive contact formed on the P-well tap, and a second conductor connected to the second contact to provide ground to the second contact. 
   
   
     3. A semiconductor structure, comprising:
 a substrate; 
 a P-doped epitaxial layer formed over the substrate, the epitaxial layer having filler cell and standard cell regions; 
 a plurality of P-doped regions on the filler cell region; 
 a plurality of N-doped portions on the filler cell region and alternating with the P-doped regions; 
 an N-doped distal linking portion on the filler cell region and connecting a first set of the N-doped portions to one another; 
 a P-doped region on the standard cell region adjacent the first set; 
 an N-doped proximal linking portion on the standard cell region and connecting a second set of the N-doped portions to one another, the N-doped portions, the N-doped distal linking portion, and the N-doped proximal linking portion jointly forming an N-doped region; and 
 a conductor connected to the N-doped region to provide a voltage potential to the N-doped region and a capacitance between the N-doped portions and the P-doped regions. 
 
   
   
     4. The semiconductor structure of  claim 3 , further comprising two transistors formed in the P-doped region and the N-doped proximal portion, respectively, over the standard cell region. 
   
   
     5. The semiconductor structure of  claim 3 , wherein the N-doped region is an N-well, further comprising an N-well tap in the N-well, having a higher N-type conductivity concentration than the N-well, a first conductive contact formed on the N-well tap, the first conductor being connected to the first contact, a P-doped epitaxial layer, a P-well, the P-doped region being connected through the P-doped epitaxial layer to the P-well, a P-well tap in the P-well having a higher P-type conductivity concentration than the P-well, a conductive contact formed on the P-well tap, and a second conductor connected to the second contact to provide ground to the second contact. 
   
   
     6. An inverter circuit, comprising:
 a P-well; 
 an NMOS transistor formed in and on the P-well; 
 an N-well having an inner region and an outer region; 
 a PMOS transistor formed in and on the inner region; 
 a plurality of P-doped regions in the outer region; 
 a ground circuit connected to the P-well and a source/drain region of the NMOS transistor; 
 a power circuit connected to the N-well and a source/drain region of the PMOS transistor; 
 a Vin circuit connected to a gate of the PMOS transistor and a gate of the NMOS transistor; and 
 a Vout circuit connected to a source/drain region of the PMOS and a source/drain region of the NMOS transistor. 
 
   
   
     7. The inverter circuit of  claim 6 , wherein the P-doped regions are located between the P-well and the NMOS transistor. 
   
   
     8. The inverter circuit of  claim 6 , wherein the P-doped regions completely surround the NMOS transistor. 
   
   
     9. The inverter circuit of  claim 6 , wherein the N-doped region leaves a plurality of P-doped regions, and the N-doped region has a plurality of portions alternating with the P-doped regions. 
   
   
     10. A bonus cell, comprising:
 a P-well; 
 two gate electrodes formed on the P-well; 
 three N-diffusion regions formed in the P-well respectively between and outside the gate electrodes on the P-well; 
 an N-well adjacent the P-well, the N-well having inner and outer regions; 
 a plurality of P-doped regions in the outer region; 
 two gate electrodes formed on the N-well; and 
 three P-diffusion regions formed in the inner regions respectively between and outside the gate electrodes on the N-well. 
 
   
   
     11. The bonus cell of  claim 10 , further comprising an N-well tap in the N-well having a higher N-type conductivity concentration than the N-well, and a first conductive contact formed on the N-well tap. 
   
   
     12. The bonus cell of  claim 11 , further comprising a P-well tap in the P-well having a higher P-type conductivity concentration than the P-well, and a second conductive contact formed on the P-well tap.