Serial to parallel conversion circuit having a shift clock frequency lower than a data transfer frequency

Abstract

A serial to parallel conversion circuit is provided. The circuit includes a shift register including flip-flops latch circuits, and control circuits. The flip-flops are connected in cascade, with a first stage flip-flop supplied with a transfer start signal that is sequentially transferred through the shift register, responsive to a shift clock signal. The latch circuits receive the output signals of the flip-flops, and latch and output a data signal, responsive to the output signals. The control circuits correspond to the flip-flops, and a first stage control circuit receives the shift clock signal and a start pulse and each remaining control circuit receives the shift clock signal and an output signal of a corresponding flip-flop. Each control circuit sets a state of a corresponding flip-flop to control a pulse width of an output signal. The frequency of said shift clock signal is set to lower than a data transfer frequency.

1. A serial to parallel conversion circuit comprising:
 a shift register including a plurality of flip-flops, connected in cascade, with a first stage flip-flop being supplied with a transfer start signal, said transfer start signal being sequentially transferred through said shift register, responsive to a shift clock signal; 
 a plurality of latch circuits, receiving respective output signals of said plurality of flip-flops, each of said latch circuits latching and outputting a data signal, serially supplied to a data line, responsive to the respective output signals; and 
 a plurality of control circuits corresponding to said plurality of flip-flops, a first stage control circuit of the plurality of control circuits receiving at least said shift clock signal and a start pulse and each remaining control circuit of the plurality of control circuits receiving at least said shift clock signal and an output signal of a corresponding upstream flip-flop, each of said control circuits setting a state of a corresponding downstream flip-flop, when, in case the output signal of a corresponding downstream flip-flop is in an active state, said shift clock signal undertakes a transition from an active state to an inactive state, so that an output signal of the corresponding downstream flip-flop is in an inactive state, to control a pulse width of said output signal; 
 wherein a frequency of said shift clock signal is set to lower than a data transfer frequency. 
 
     
     
       2. The serial to parallel conversion circuit according to  claim 1 , wherein each of said plurality of control circuits comprises:
 a circuit for generating a clock signal supplied to a clock input terminal of a corresponding downstream flip-flop, responsive to a transition to an activated state of said shift clock signal, based on a data signal supplied to a data input terminal of said corresponding downstream flip-flop, on an output signal of said corresponding downstream flip-flop, and on said shift clock signal; and 
 a circuit for generating a signal for resetting said corresponding downstream flip-flop based on an output signal of said corresponding downstream flip-flop, on said shift clock signal, and on a reset signal which control a resetting of said shift register; wherein said circuit for generating the signal for resetting said corresponding downstream flip-flop resets said corresponding downstream flip-flop in a case where said reset signal is in an active state, and in a case where said reset signal is in an inactive state, the output signal of said corresponding downstream flip-flop is in an active state and said shift clock signal is in an inactive state. 
 
     
     
       3. The serial to parallel conversion circuit according to  claim 2 , further comprising:
 a frequency dividing circuit, which receives a data transfer clock signal and frequency divides said data transfer clock signal to generate a frequency divided clock signal having a corrected phase. 
 
     
     
       4. The serial to parallel conversion circuit according to  claim 1 , wherein each of said plurality of latch circuits is a D latch or an edge triggered D flip-flop. 
     
     
       5. A semiconductor device comprising the serial to parallel conversion circuit as defined in  claim 1 . 
     
     
       6. A serial to parallel conversion circuit comprising:
 a shift register including a plurality of flip-flops, a data input terminal of a first stage flip-flop being supplied with a transfer start pulse signal for controlling a start of a data transfer, data input terminals of remaining stage flip-flops of the plurality of flip-flops being supplied with output signals of respective preceding stage flip-flops, said shift register sequentially transferring said transfer start pulse responsive to a shift clock signal common to clock terminals of said plurality of flip-flops from a clock line; 
 a plurality of latch circuits, receiving pulse signals sequentially output from output terminals of said plurality of flip-flops, said latch circuits having data input terminals connected in common to a data line, each of said latch circuits latching and outputting a data signal serially transmitted on said data line, responsive to said pulse signals; 
 neighboring flip-flops of said plurality of flip-flops sampling and outputting signals input to respective data input terminals of the neighboring flip-flops, rising and falling edges, respectively, of the shift clock signal supplied from said clock line; and 
 a plurality of control circuits provided upstream of respective flip-flops of said plurality of flip-flops, a first stage control circuit of the plurality of control circuits for receiving at least the shift clock signal and the transfer start pulse signal and each remaining control circuit of the plurality of control circuits for receiving at least the shift clock signal and an output signal of a corresponding upstream flip-flop, each of said control circuits resetting a corresponding downstream flip-flop to inactivate an output signal of said corresponding downstream flip-flop to control a pulse width of said output signal, when, in case the output signal of said corresponding downstream flip-flop is in an active state, the shift clock signal supplied to said corresponding downstream flip-flop undertakes a transition from an active state to an inactive state; 
 wherein a frequency of said shift clock signal is set to lower than a data transfer frequency. 
 
     
     
       7. The serial to parallel conversion circuit according to  claim 6 , wherein each of said plurality of control circuits comprises:
 a circuit for generating a clock signal supplied to a clock input terminal of a corresponding downstream flip-flop, responsive to a transition to an activated state of said shift clock signal, based on a data signal supplied to a data input terminal of said corresponding downstream flip-flop, on an output signal of said corresponding downstream flip-flop, and on said shift clock signal; and 
 a circuit for generating a signal for resetting said corresponding downstream flip-flop based on an output signal of said corresponding downstream flip-flop, on said shift clock signal, and on a reset signal which controls a resetting of said shift register; wherein said circuit for generating the signal for resetting said corresponding downstream flip-flop resets said corresponding downstream flip-flop in a case where said reset signal is in an active state, and in a case where said reset signal is in an inactive state, the output signal of said corresponding downstream flip-flop is in an active state and said shift clock signal is in an inactive state. 
 
     
     
       8. The serial to parallel conversion circuit according to  claim 7 , further comprising:
 a frequency dividing circuit, which receives a data transfer clock signal and frequency divides said data transfer clock signal to generate, a frequency divided clock signal having a corrected phase. 
 
     
     
       9. The serial to parallel conversion circuit according to  claim 6 , further comprising:
 a frequency dividing circuit, which receives a data transfer clock signal and frequency divides said data transfer clock signal to generate a frequency divided clock signal having a corrected phase. 
 
     
     
       10. The serial to parallel conversion circuit according to  claim 9 , further comprising:
 a circuit which receives data and a pulse signal for starting the data transfer and outputs said transfer start pulse signal to the data input terminal of the first stage flip-flop of said shift register and outputs sequentially said data to said data line responsive to said data transfer clock signal. 
 
     
     
       11. The serial to parallel conversion circuit according to  claim 6 , wherein each of said plurality of latch circuits is a D latch or an edge triggered D flip-flop. 
     
     
       12. A serial to parallel conversion circuit comprising:
 a shift register including a plurality of flip-flops, a data input terminal of a first stage flip-flop of the plurality of flip-flops being supplied with a transfer start pulse signal for controlling a start of a data transfer, data input terminals of a second stage flip-flop and following stage flip-flops of the plurality of flip-flops being supplied with output signals of respective preceding stage flip-flops, said shift register sequentially transferring said transfer start pulse signal responsive to a shift clock signal to clock terminals of said plurality of flip-flops from a clock line; and 
 a plurality of latch circuits receiving pulse signals, sequentially output from output terminals of said plurality of flip-flops, said latch circuits having data input terminals connected in common to a data line, each of said latch circuits latching and outputting a data signal, responsive to the pulse signals; 
 neighboring flip-flops of said plurality of flip-flops sampling and outputting signals input to respective data input terminals of the neighboring flip-flops, on rising and falling edges, respectively, of the shift clock signal supplied from said clock line; 
 wherein a frequency of said shift clock signal is set lower than a data transfer frequency. 
 
     
     
       13. The serial to parallel conversion circuit according to  claim 12 , further comprising:
 a frequency dividing circuit, which receives a data transfer clock signal and frequency divides said data transfer clock signal to generate a frequency divided clock signal having a corrected phase. 
 
     
     
       14. The serial to parallel conversion circuit according to  claim 12 , wherein each of said plurality of latch circuits is a D latch or an edge triggered D flip-flop.