Selectable application of offset to dynamically controlled voltage supply

Abstract

An electronic system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a first circuit for providing a first value indicating a first potential capability of operational speed of at least one path in the plurality of circuit paths and a second circuit for providing a second value for indicating a second potential capability of operational speed of the at least one path in the plurality of circuit paths. The system further comprises circuitry for adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value.

1. An electronic system, comprising:
 a plurality of circuit paths, wherein each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply; 
 a first circuit for providing a first value indicating a first potential capability of operational speed of at least one path in the plurality of circuit paths; 
 a second circuit for providing a second value for indicating a second potential capability of operational speed of the at least one path in the plurality of circuit paths; and 
 circuitry for adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value; and 
 wherein the at least one path in the plurality of paths comprises a path through a memory device. 
 
   
   
     2. The system of  claim 1  and further comprising the voltage supply. 
   
   
     3. The system of  claim 1  wherein the plurality of circuit paths, the first circuit, the second circuit, and the circuitry for adjusting are integrated in a single integrated circuit device. 
   
   
     4. The system of  claim 1  wherein the memory device comprises a static random access memory device. 
   
   
     5. The system of  claim 1 :
 wherein the first circuit comprises a NOR oscillator; and 
 wherein the second circuit comprises an NAND oscillator. 
 
   
   
     6. The system of  claim 4  wherein the static random access memory device comprises a plurality of cells, and each cell comprises:
 a first p-channel transistor having a source coupled to receive the system voltage, a drain connected to a first node, and a gate connected to a second node; 
 a second p-channel transistor having a source coupled to receive the system voltage, a drain connected to the second node, and a gate connected to the first node; 
 a first n-channel transistor having a source coupled to receive a voltage less than the system voltage, a drain connected to the first node, and a gate connected to the gate of the first p-channel transistor; and 
 a second n-channel transistor having a source coupled to receive the voltage less than the system voltage, a drain connected to the second node, and a gate connected to the gate of the second p-channel transistor. 
 
   
   
     7. The system of  claim 6  and further comprising:
 a first selective discharge path coupled between the first node and the voltage less than the system voltage; and 
 a second selective discharge path coupled between the second node and the voltage less than the system voltage; and 
 wherein each of the first and second selective discharge paths comprises a source/drain path of at least one n-channel transistor. 
 
   
   
     8. The system of  claim 1  wherein the first circuit for providing the first value is for providing a value that is more sensitive to PMOS operational speed in the system as compared to NMOS operational speed in the system. 
   
   
     9. The system of  claim 1  wherein the second circuit for providing the second value is for providing a value that is more sensitive to NMOS operational speed in the system as compared to PMOS operational speed in the system. 
   
   
     10. The system of  claim 1  wherein a relation between the first value and the second value comprises a ratio between the first value to the second value. 
   
   
     11. The system of  claim 10  wherein the circuitry for adjusting adjusts in response to an extent to which the ratio exceeds a predetermined value. 
   
   
     12. The system of  claim 10  wherein the circuitry for adjusting adjusts in response to a linear multiplier times an extent to which the ratio exceeds a predetermined value. 
   
   
     13. The system of  claim 12  wherein the predetermined value is approximately 0.35. 
   
   
     14. The system of  claim 10 :
 wherein the first circuit comprises a NOR oscillator; and 
 wherein the second circuit comprises an NAND oscillator. 
 
   
   
     15. The system of  claim 10 :
 wherein the plurality of circuit paths comprises circuitry for receiving and responsive to a system clock signal; 
 wherein the circuitry for adjusting comprises circuitry for comparing the first value and the second value with the system clock signal as it switches over a period of time; and 
 wherein the circuitry for adjusting the system voltage is further for adjusting the system voltage in response to the circuitry for comparing. 
 
   
   
     16. The system of  claim 1  wherein the circuitry for adjusting the system voltage is further for adjusting the system voltage to decrease supplied power in response to a determination by a circuitry for comparing determining that the first value and the second value represent operations speeds that exceed that of a system clock signal. 
   
   
     17. The system of  claim 1  wherein the circuitry for adjusting the system voltage is further for adjusting the system voltage to increase supplied power in response to a determination by a circuitry for comparing determining that either the first value or the second value represents an operational speed that is below that of a system clock signal. 
   
   
     18. The system of  claim 17  wherein the circuitry for comparing comprises circuitry for comparing either a scaled version of the first value or a scaled version of the second value to the system clock signal. 
   
   
     19. The system of  claim 16 :
 wherein the first circuit comprises a NOR oscillator; and 
 wherein the second circuit comprises an NAND oscillator. 
 
   
   
     20. The system of  claim 19  wherein the relation between the first value and the second value comprises a ratio between the first value to the second value. 
   
   
     21. The system of  claim 20  wherein the circuitry for adjusting adjusts in response to an extent to which the ratio exceeds a predetermined value. 
   
   
     22. The system of  claim 21  wherein the circuitry for adjusting adjusts in response to a linear multiplier times an extent to which the ratio exceeds the predetermined value. 
   
   
     23. The system of  claim 22  wherein the predetermined value is approximately 0.35. 
   
   
     24. A method of operating an electronic system comprising a plurality of circuit paths, wherein each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply, the method comprising:
 providing a first value indicating a first potential capability of operational speed of at least one path in the plurality of circuit paths; 
 providing a second value for indicating a second potential capability of operational speed of the at least one path in the plurality of circuit paths; and 
 adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value; and 
 wherein the at least one path in the plurality of paths comprises a path through a memory device. 
 
   
   
     25. The method of  claim 24  wherein the memory device comprises a static random access memory device. 
   
   
     26. The method of  claim 25 :
 wherein the step of providing a first value comprises providing the first value from a NOR oscillator; and 
 wherein the step of providing a second value comprises providing the second value from an NAND oscillator. 
 
   
   
     27. The method of  claim 25  wherein the step of providing a first value is for providing a value that is more sensitive to PMOS operational speed in the system as compared to NMOS operational speed in the system. 
   
   
     28. The method of  claim 27  wherein the step of providing a second value is for providing a value that is more sensitive to NMOS operational speed in the system as compared to PMOS operational speed in the system. 
   
   
     29. The method of  claim 28  wherein the relation between the first value and the second value comprises a ratio between the first value to the second value. 
   
   
     30. The method of  claim 29  wherein the step of adjusting adjusts in response to an extent to which the ratio exceeds a predetermined value. 
   
   
     31. The method of  claim 29  wherein the step of adjusting adjusts in response to a linear multiplier times an extent to which the ratio exceeds a predetermined value. 
   
   
     32. The method of  claim 29 :
 wherein the plurality of circuit paths comprises circuitry for receiving and responsive to a system clock signal; 
 wherein the step of adjusting comprises comparing the first value and the second value with the system clock signal as it switches over a period of time; and 
 wherein the step of adjusting the system voltage is further for adjusting the system voltage in response to circuitry for comparing the first and second values. 
 
   
   
     33. The method of  claim 32  wherein the step of adjusting the system voltage is further for adjusting the system voltage to decrease supplied power in response to a determination by the circuitry for comparing determining that the first value and the second value represent operations speeds that exceed that of the system clock signal. 
   
   
     34. The method of  claim 32  wherein the step of adjusting the system voltage is further for adjusting the system voltage to increase supplied power in response to a determination by the circuitry for comparing determining that either the first value or the second value represents an operational speed that is below that of the system clock signal. 
   
   
     35. The method of  claim 24  wherein the relation between the first value and the second value comprises a ratio between the first value to the second value.