Memory controller hub interface

Abstract

A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

1. A computer chip comprising:
 an internal graphics subsystem adapted to perform graphics operations on data; and interface circuitry adapted selectively to couple the internal graphics subsystem to a local memory through electrical connectors and to couple the computer chip to an external graphics controller through the same electrical connectors, wherein the local memory is to provide graphics memory for use by the internal graphics subsystem. 
 
   
   
     2. The computer chip of  claim 1  wherein the interface circuitry comprises a cache interface for coupling the graphics subsystem to a local memory and a controller interface for coupling the computer chip to a graphics controller. 
   
   
     3. The computer chip of  claim 2  wherein the controller interface is adapted to couple the computer chip to the graphics controller though an accelerated graphics port (AGP). 
   
   
     4. The computer chip of  claim 2  wherein the local memory includes an AGP inline memory module. 
   
   
     5. The computer chip of  claim 2  wherein the cache interface is adapted to couple the graphics subsystem to the local memory though an accelerated graphics port (AGP). 
   
   
     6. The computer chip of  claim 1  wherein the electrical connectors are adapted for use by the interface circuitry to transfer signals between the graphics subsystem and a local memory and for use by the interface circuitry to transfer signals between the computer chip and a graphics controller. 
   
   
     7. A computer system comprising:
 a CPU; 
 a display device; 
 a system memory, the system memory adapted to store video data and non-video data; and 
 a computer chip coupled to the CPU and coupled to the system memory, the computer chip comprising:
 an internal graphics subsystem adapted to perform graphics operations on graphics data; and 
 interface circuitry adapted selectively to couple the internal graphics subsystem to a local memory through electrical connectors and to couple the computer chip to an external graphics controller through the same electrical connectors, wherein the local memory is to provide graphics memory for use by the internal graphics subsystem. 
 
 
   
   
     8. The computer system of  claim 7  wherein the interface circuitry comprises a cache interface for coupling the graphics subsystem to a local memory through electrical connectors and a controller interface for coupling the computer chip to a graphics controller through the electrical connectors. 
   
   
     9. The computer system of  claim 7  wherein the electrical connectors are adapted for use by the cache interface to transfer signals between the graphics subsystem and a local memory and for use by the controller interface to transfer signals between the computer chip and a graphics controller. 
   
   
     10. The computer system of  claim 7  wherein the controller interface is adapted to couple the computer chip to a graphics controller though an accelerated graphics port (AGP). 
   
   
     11. The computer system of  claim 7  wherein the local memory includes an AGP inline memory module. 
   
   
     12. The computer system of  claim 7  wherein the cache interface is adapted to couple the internal graphics subsystem to a local memory though an accelerated graphics port (AGP).