Method and apparatus for sigma-delta delay control in a delay-locked-loop

Abstract

Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

1. A delay control method for a Delay-Locked-Loop circuit that employs a delay line to generate a clock signal based on a reference signal, comprising:
 generating a first value if said clock signal has a phase lead relative to said reference signal; 
 generating a second value if said clock signal has a phase lag relative to said reference signal; 
 accumulating said first and second values to generate an N bit digital word; 
 reducing said N bit digital word to an M bit digital word, where M is less than N, wherein said reducing step is performed by a sigma-delta modulator; and 
 converting said M bit digital word to an analog bias signal that adjusts a phase offset between said reference signal and said clock signal. 
 
   
   
     2. The method of  claim 1 , further comprising the step of filtering high frequency quantization noise generated by said sigma-delta modulator. 
   
   
     3. The method of  claim 1 , wherein said converting step is performed by a digital-to-analog converter. 
   
   
     4. The method of  claim 3 , wherein said digital-to-analog converter is a master/slave digital-to-analog converter. 
   
   
     5. The method of  claim 4 , wherein said master/slave digital-to-analog converter is comprised of a master digital-to-analog converter and a slave digital-to-analog converter and wherein each step of said slave digital-to-analog converter is proportional to a value generated by said master digital-to-analog converter. 
   
   
     6. The method of  claim 5 , further comprising the steps of setting said master digital-to-analog converter to a maximum value and maintaining said slave digital-to-analog converter at a mid-range value upon a reset. 
   
   
     7. The method of  claim 5 , further comprising the steps of maintaining a value of said master digital-to-analog converter and allowing a value of said slave digital-to-analog converter to vary upon detection of a predefined event. 
   
   
     8. The method of  claim 7 , wherein said predefined event is a change in direction of a phase control signal. 
   
   
     9. A delay control method for a Delay-Locked-Loop circuit that employs a delay line to generate a clock signal based on a reference signal, comprising:
 generating a first value if said clock signal has a phase lead relative to said reference signal; 
 generating a second value if said clock signal has a phase lag relative to said reference signal; 
 accumulating said first and second values to generate a first digital word; 
 applying said first digital word to a sigma-delta modulator to generate a second digital word having high frequency quantization noise; 
 converting said second digital word to an analog bias signal that adjusts a phase offset between said reference signal and said clock signal; and 
 applying said analog bias signal to a low pass filter to reduce said high frequency quantization noise. 
 
   
   
     10. The method of  claim 9 , wherein said converting step is performed by a digital-to-analog converter. 
   
   
     11. The method of  claim 10 , wherein said digital-to-analog converter is a master/slave digital-to-analog converter. 
   
   
     12. A Delay-Locked-Loop circuit that employs a delay line to generate a clock signal based on a reference signal, comprising:
 a phase comparator generating a first value if said clock signal has a phase lead relative to said reference signal and a second value if said clock signal has a phase lag relative to said reference signal; 
 a digital accumulator for accumulating said first and second values to generate an N bit digital word; 
 a sigma-delta modulator for generating an M bit digital word based on said N bit digital word; and 
 a digital-to-analog converter for converting said M bit digital word to an analog bias signal that adjusts a phase offset between said reference signal and said clock signal. 
 
   
   
     13. The Delay-Locked-Loop circuit of  claim 12 , further comprising a low pass filter to filter high frequency quantization noise generated by said sigma-delta modulator. 
   
   
     14. The Delay-Locked-Loop circuit of  claim 12 , wherein said digital-to-analog converter is a master/slave digital-to-analog converter. 
   
   
     15. The Delay-Locked-Loop circuit of  claim 14 , wherein said master/slave digital-to-analog converter is comprised of a master digital-to-analog converter and a slave digital-to-analog converter and wherein each step of said slave digital-to-analog converter is proportional to a value generated by said master digital-to-analog converter. 
   
   
     16. The Delay-Locked-Loop circuit of  claim 15 , wherein said master digital-to-analog converter is set to a maximum value and said slave digital-to-analog converter is maintained at a mid-range value upon a reset. 
   
   
     17. The Delay-Locked-Loop circuit of  claim 15 , wherein a value of said master digital-to-analog converter is maintained and a value of said slave digital-to-analog converter is allowed to vary upon detection of a predefined event. 
   
   
     18. The Delay-Locked-Loop circuit of  claim 17 , wherein said predefined event is a change in direction of a phase control signal. 
   
   
     19. The Delay-Locked-Loop circuit of  claim 17 , further comprising a finite state machine for detecting said predefined event. 
   
   
     20. A Delay-Locked-Loop circuit that employs a delay line to generate a clock signal based on a reference signal, comprising:
 a phase comparator generating a first value if said clock signal has a time lead relative to said reference signal and a second value if said clock signal has a time lag relative to said reference signal; 
 a digital accumulator for accumulating said first and second values to generate an N bit digital word; and 
 a master/slave digital-to-analog converter for generating an analog bias signal that adjusts a time delay between said reference signal and said clock signal, wherein said master/slave digital-to-analog converter is comprised of a master digital-to-analog converter path and a slave digital-to-analog converter path and wherein said slave digital-to-analog converter path comprises a sigma-delta modulator for generating an M bit digital word based on said N bit digital word, wherein said M bit digital word is applied to a slave digital-to-analog converter. 
 
   
   
     21. The Delay-Locked-Loop circuit of  claim 20 , further comprising a low pass filter to filter high frequency quantization noise generated by said sigma-delta modulator. 
   
   
     22. The Delay-Locked-Loop circuit of  claim 20 , wherein said master digital-to-analog converter is set to a maximum value and said slave digital-to-analog converter is maintained at a mid-range value upon a reset. 
   
   
     23. The Delay-Locked-Loop circuit of  claim 20 , wherein a value of said master digital-to-analog converter is maintained and a value of said slave digital-to-analog converter is allowed to vary upon detection of a predefined event. 
   
   
     24. The Delay-Locked-Loop circuit of  claim 23 , wherein said predefined event is a change in direction of a phase control signal.