Digital/analog converter

Abstract

The present invention relates to a digital/analog converter. The digital/analog converter includes a divided-voltage generating section that divides a reference supply voltage through the voltage distribution; a decoder section that receives a digital signal so as to output a decoded selection signal; a first divided-voltage selecting section that selects and outputs a plurality of divided voltages among the divided-voltages generated from the divided-voltage generating section on the basis of the selection signal output from the decoder section; a second divided-voltage selecting section that selects and outputs a plurality of divided-voltages among the divided-voltages output from the first divided-voltage selecting section on the basis of the selection signal output from the decoder section; a divided-voltage storing section that charges and discharges the plurality of divided-voltages output from the second divided-voltage selecting section; a third divided-voltage selecting section that selects a predetermined voltage among the divided-voltages discharged from the divided-voltages storing section on the basis of the selection signal output from the decoder; and a voltage output section that outputs the predetermined voltage selected from the third divided-voltage selecting section.

1. A digital/analog converter comprising:
 a divided-voltage generating section that divides a reference supply voltage into a plurality of divided-voltages through a voltage distribution comprising a plurality of nodes; 
 a decoder section that receives a digital signal so as to output a decoded selection signal; 
 a first divided-voltage selecting section that selects a first set of nodes from the divided-voltage generating section and outputs a first set of divided voltages based upon the decoded selection signal; 
 a second divided-voltage selecting section that selects and outputs a second set of divided-voltages from among the first set of divided-voltages on the basis of the decoded selection signal; 
 a divided-voltage storing section that charges and discharges the second set of divided-voltages output from the second divided-voltage selecting section; 
 a third divided-voltage selecting section that selects a predetermined voltage among the divided-voltages discharged from the divided-voltage storing section on the basis of the decoded selection signal; and 
 a voltage output section that outputs the predetermined voltage selected from the third divided-voltage selecting section; 
 wherein the first divided-voltage selecting section includes a plurality of switches connected to the plurality of nodes formed in the divided-voltage generating section; 
 wherein the second divided-voltage selecting section includes a plurality of switches connected to the first set of selected nodes, and to nodes adjacent to the first set of selected nodes; and 
 wherein a voltage associated with the first set of selected nodes is selected as a high voltage, and a voltage associated with the nodes adjacent to the first set of selected nodes is selected as a low voltage. 
 
   
   
     2. The digital/analog convener according to  claim 1 ,
 wherein the divided-voltage generating section is composed of a plurality of serially-connected resistance elements. 
 
   
   
     3. The digital/analog converter according to  claim 1 ,
 wherein the first divided-voltage selecting section is composed of a plurality of switches which are connected to the plurality of nodes formed in the divided-voltage generating section. 
 
   
   
     4. The digital/analog converter according to  claim 3 ,
 wherein the plurality of switches are implemented of transistors. 
 
   
   
     5. The digital/analog converter according to  claim 1 ,
 wherein the second divided-voltage selecting section is composed of a plurality of switches connected to the first set of selected nodes and to the nodes adjacent to the first set of selected nodes. 
 
   
   
     6. The digital/analog converter according to  claim 1 ,
 wherein the divided-voltage storing section includes: 
 a first capacitor that charges and discharges the high voltage; 
 a second capacitor that charge and discharges the low voltage; 
 a first switch that is connected to the first capacitor and the node having a divided-voltage selected as the high voltage; 
 a second switch that is connected to the second capacitor and the node having a divided-voltage selected as the low voltage; 
 a third switch that is connected to the first capacitor and the third divided-voltage selecting section; and 
 a fourth switch that is connected to the second capacitor and the third divided-voltage selecting section. 
 
   
   
     7. The digital/analog converter according to  claim 6 ,
 wherein the third divided-voltage selecting section includes: 
 fifth and sixth switches that are connected to the high or low voltage; 
 a first resistor that is connected to the fifth switch so as to receive the high or low voltage; 
 a second resistor that is connected to the sixth switch so as to receive the high or low voltage; and 
 a third resistor that receives the low voltage. 
 
   
   
     8. The digital/analog converter according to  claim 7 ,
 wherein the first to third resistors are connected in parallel. 
 
   
   
     9. The digital/analog converter according to  claim 8 ,
 wherein the second and third resistors have the same resistance value, and the first resistor has one half of the resistance value of the second and third resistors. 
 
   
   
     10. The digital/analog converter according to  claim 7 ,
 wherein the fifth and sixth switches are implemented of transistors. 
 
   
   
     11. The digital/analog converter according to  claim 6 ,
 wherein the first to fourth switches are implemented of transistors. 
 
   
   
     12. The digital/analog converter according to  claim 1 ,
 wherein the voltage output section is composed of an output buffer which buffers and outputs a predetermined voltage selected by the third divided-voltage selecting section. 
 
   
   
     13. The digital/analog converter according to  claim 10 ,
 wherein the predetermined voltage is fed back to the output buffer, as a side input.