Method for fabricating semiconductor device

Abstract

A method for fabricating a semiconductor device includes forming a doped polysilicon layer on a semiconductor substrate forming an oxide film for device isolation in a predetermined region of the doped polysilicon layer and the semiconductor substrate, forming an etch stop layer on the oxide film for device isolation and the doped polysilicon layer, etching a predetermined region of the etch stop layer, the doped polysilicon layer and the semiconductor substrate to form a trench defining a gate region, depositing a gate oxide film on the gate region, forming a gate electrode layer and a hard mask layer filling the trench, and polishing the gate electrode layer and the hard mask layer to expose the etch stop layer and to form a gate in the gate region.

1. A method for fabricating a semiconductor device, comprising:
 forming a doped polysilicon layer on a semiconductor substrate; 
 forming an oxide film for device isolation in a predetermined region of the doped polysilicon layer and the semiconductor substrate; 
 forming an etch stop layer on the oxide film for device isolation and the doped polysilicon layer; 
 etching a predetermined region of the etch stop layer, the doped polysilicon layer and the semiconductor substrate to form a trench defining a gate region; 
 depositing a gate oxide film on the gate region; 
 forming a gate electrode layer and a hard mask layer filling the trench; and 
 polishing the gate electrode layer and the hard mask layer to expose the etch stop layer and to form a gate in the gate region. 
 
   
   
     2. The method according to  claim 1 , wherein the polishing is chemical-mechanical polishing. 
   
   
     3. The method according to  claim 1 , wherein forming a doped polysilicon layer on a semiconductor substrate comprises:
 forming an undoped polysilicon layer on the semiconductor substrate; and 
 performing an ion implantation process on the undoped polysilicon layer. 
 
   
   
     4. The method according to  claim 1 , wherein forming a doped polysilicon layer on a semiconductor substrate comprises:
 forming the doped polysilicon layer using a Si source gas and an impurity source gas. 
 
   
   
     5. The method according to  claim 1 , wherein the gate electrode layer comprises a stacked structure of a gate polysilicon layer and a gate metal layer. 
   
   
     6. The method according to  claim 5 , wherein the gate metal layer comprises a metal selected from the group consisting of W, Co, Ta, Mo, Hf, Nb, V, Zr, silicide thereof and combinations thereof. 
   
   
     7. The method according to  claim 1 , further comprising:
 forming a first insulating film on the etch stop layer and the gate; 
 forming a bit line contact plug to the doped polysilicon layer in a predetermined region of the first insulating film and the etch stop layer; 
 forming a second insulating film on the first insulating film including the bit line contact plug; 
 forming a storage node contact plug in a predetermined region of the second insulating film, the first insulating film and the etch stop layer; 
 forming a lower electrode layer on the second insulating film and the storage node contact plug; and 
 depositing a dielectric layer and an upper electrode layer over the lower electrode layer to form a capacitor. 
 
   
   
     8. A method for fabricating a semiconductor device, comprising:
 forming a polysilicon layer on a semiconductor substrate; 
 etching a predetermined region of the polysilicon layer and the semiconductor substrate to form a trench for device isolation; 
 forming an oxide film filling the trench for device isolation; 
 forming an etch stop layer on the oxide film and the polysilicon layer; 
 etching a predetermined region of the etch stop layer, the polysilicon layer and the semiconductor substrate to form a trench defining a gate region; 
 depositing a gate oxide film on the gate region; 
 forming a gate electrode layer and a hard mask layer filling the trench; and 
 polishing the gate electrode layer and the hard mask layer to expose the etch stop layer and to form a gate in the gate region. 
 
   
   
     9. The method according to  claim 8 , wherein the polysilicon is a doped polysilicon having impurities selected from the group consisting of P, As and a combination thereof. 
   
   
     10. The method according to  claim 8 , wherein forming a polysilicon layer on a semiconductor substrate comprises:
 forming an undoped polysilicon layer on the semiconductor substrate; and 
 performing an ion implantation process on the undoped polysilicon layer. 
 
   
   
     11. The method according to  claim 8 , wherein forming a polysilicon layer on a semiconductor substrate comprises:
 forming a doped polysilicon layer using a Si source gas and an impurity source gas. 
 
   
   
     12. The method according to  claim 8 , wherein the gate electrode layer comprises a stacked structure of a gate polysilicon layer and a gate metal layer. 
   
   
     13. The method according to  claim 12 , wherein the gate metal layer comprises a metal selected from the group consisting of W, Co, Ta, Mo, Hf, Nb, V, Zr, silicide thereof and combinations thereof. 
   
   
     14. The method according to  claim 8 , wherein the polishing is chemical-mechanical polishing. 
   
   
     15. The method according to  claim 8 , further comprising:
 forming a first insulating film on the etch stop layer and the gate; 
 forming a bit line contact plug to the doped polysilicon layer in a predetermined region of the first insulating film and the etch stop layer; 
 forming a second insulating film on the first insulating film including the bit line contact plug; 
 forming a storage node contact plug in a predetermined region of the second insulating film, the first insulating film and the etch stop layer; 
 forming a lower electrode layer on the second insulating film and the storage node contact plug; and 
 depositing a dielectric layer and an upper electrode layer over the lower electrode layer to form a capacitor. 
 
   
   
     16. A method for fabricating a semiconductor device, comprising:
 forming a doped polysilicon layer on a semiconductor substrate; 
 forming an etch stop layer on the doped polysilicon layer; 
 etching a predetermined region of the etch stop layer, the doped polysilicon layer and the semiconductor substrate to form a trench defining a gate region; 
 depositing a gate oxide film on the gate region; 
 forming a gate electrode layer and a hard mask layer filling the trench; 
 polishing the gate electrode layer and the hard mask layer to expose the etch stop layer and to form a gate in the gate region; 
 forming a first insulating film on the etch stop layer and the gate; and 
 forming a contact plug to the doped polysilicon layer in a predetermined region of the first insulating film and the etch stop layer. 
 
   
   
     17. The method according to  claim 16 , wherein the polishing is chemical-mechanical polishing. 
   
   
     18. The method according to  claim 16 , wherein forming a doped polysilicon layer on a semiconductor substrate comprises:
 forming an undoped polysilicon layer on the semiconductor substrate; and 
 performing an ion implantation process on the undoped polysilicon layer. 
 
   
   
     19. The method according to  claim 16 , wherein forming a doped polysilicon layer on a semiconductor substrate-comprises:
 forming the polysilicon layer using a Si source gas and an impurity source gas. 
 
   
   
     20. The method according to  claim 16 , wherein the gate electrode layer comprises a stacked structure of a gate polysilicon layer and a gate metal layer.