P
US7333379B2ExpiredUtilityPatentIndex 53

Balanced sense amplifier circuits with adjustable transistor body bias

Assignee: IBMPriority: Jan 12, 2006Filed: Jan 12, 2006Granted: Feb 19, 2008
Est. expiryJan 12, 2026(expired)· nominal 20-yr term from priority
Inventors:RAMADURAI VINODSEITZER DARYL MICHAEL
G11C 29/028G11C 29/026G11C 7/065G11C 2207/2254G11C 29/02
53
PatentIndex Score
3
Cited by
10
References
1
Claims

Abstract

Structures of balanced sense amplifier circuits and methods for operating the same. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively. The structure also comprises a control circuit, which is electrically coupled to the first and second transistor bodies. The structure further comprises a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit. The testing circuit is capable of determining whether strengths of the first and second transistors are different. In response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first transistor body.

Claims

exact text as granted — not AI-modified
1. A circuit adjusting method, comprising:
 providing a digital circuit, which includes:
 (a) a reading circuit, which includes a first transistor and a second transistor, wherein the first and second transistors comprise: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively, 
 (b) a control circuit, which is electrically coupled to the first and second transistor bodies, respectively, and 
 (c) a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit; 
 
 using the testing circuit to determine, for a first balanced determination round, whether strengths of the first and second transistors are different; and 
 in response to the testing circuit determining that the strengths of the first and second transistors are different, using the testing circuit to cause the control circuit to adjust the voltage of the first transistor body for a first time,
 wherein the control circuit comprises a multiplexer, 
 wherein the multiplexer includes a first multiplexer output node and a second multiplexer output node, 
 wherein the first multiplexer output node is electrically coupled to the first transistor body, and 
 wherein the second multiplexer output node is electrically coupled to the second transistor body.

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