Semiconductor package and method for manufacturing the same

Abstract

A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.

1. A semiconductor package comprising:
 a first semiconductor chip having an active surface, a back surface and a plurality of pads disposed on the active surface; 
 a first substrate layer formed on the active surface of the first semiconductor chip and comprising a plurality of first contacts electrically connected to the pads, wherein the first substrate layer has a first surface and a second surface opposite to the first surface, and the second surface disposed on the active surface of the first semiconductor chip; 
 a second substrate layer formed on the first surface of the first substrate layer and comprising a plurality of second contacts electrically connected to the first contacts, wherein the second substrate layer has a shoulder that exposes out a part of the first surface of the first substrate layer, and the part of the first surface of the first substrate layer defines a component area; and 
 a component disposed on the component area. 
 
   
   
     2. The semiconductor package as claimed in  claim 1 , wherein the first substrate layer further comprises at least one first dielectric layer and a plurality of first conductive traces disposed on the first dielectric layer for electrically connecting the first contacts to the pads. 
   
   
     3. The semiconductor package as claimed in  claim 1 , wherein the second substrate layer further comprises at least one second dielectric layer and a plurality of second conductive traces disposed on the second dielectric layer for electrically connecting the second contacts to the first contacts. 
   
   
     4. A semiconductor package comprising:
 a first semiconductor chip having an active surface, a back surface and a plurality of pads disposed on the active surface; 
 a first substrate layer formed on the active surface of the first semiconductor chip and comprising a plurality of first contacts electrically connected to the pads, wherein the first substrate layer has a first surface and a second surface opposite to the first surface, and the second surface disposed on the active surface of the first semiconductor chip; and 
 a second substrate layer formed on the first surface of the first substrate layer and comprising a plurality of second contacts electrically connected to the first contacts, wherein the second substrate layer exposes out a part of the first surface of the first substrate layer, 
 wherein the second substrate layer has a shoulder formed on the first surface of the first substrate layer; and 
 the semiconductor package further comprises at least one second semiconductor chip disposed on the shoulder. 
 
   
   
     5. The semiconductor package as claimed in  claim 4 , further comprising a plurality of second semiconductor chips stacked on the shoulder. 
   
   
     6. The semiconductor package as claimed in  claim 4 , further comprising a plurality of second semiconductor chips parallel disposed on the shoulder. 
   
   
     7. The semiconductor package as claimed in  claim 4 , further comprising a molding compound encapsulating the second semiconductor chip. 
   
   
     8. The semiconductor package as claimed in  claim 4 , further comprising at least one passive component disposed on the shoulder. 
   
   
     9. The semiconductor package as claimed in  claim 1 , further comprising a heat spreader adhering to the back surface of the first semiconductor chip. 
   
   
     10. The semiconductor package as claimed in  claim 1 , further comprising a plurality of exterior contacts disposed on the contacts of the second substrate layer for electrically connecting to a circuit device. 
   
   
     11. The semiconductor package as claimed in  claim 1 , wherein the component is a second semiconductor chip. 
   
   
     12. The semiconductor package as claimed in  claim 1 , wherein the component is a passive component.