Programmable scrambler and De-scrambler for digital telephony equipment

Abstract

A scrambler circuit for digital telephony equipment receives a sequence of input bits, generates the sequence of output bits based on the input bits and stores the sequence of output bits. The generating of the sequence of output bits includes selecting at least one of the stored output bits in accordance with contents of a mask register, and applying a logic operation to a current input bit and the selected at least one stored output bit to provide a current output bit.

1. An apparatus comprising:
 an interface to be coupled to an item of telephony equipment; and 
 a scrambler coupled to the interface to provide an output signal to the interface, the scrambler including:
 a logic circuit having a plurality of inputs and an output, one of said inputs for receiving an input signal to be scrambled by said scrambler, said input signal including a sequence of input bits, said output for supplying said output signal to said interface, said output signal including output bits; 
 a shift register coupled to the output of the logic circuit and having a plurality of taps, said shift register for storing ones of said output bits; 
 a plurality of gates each having a respective input coupled to one of the taps and a respective output coupled to a respective one of the inputs of the logic circuit; and 
 a mask register coupled to the plurality of gates and capable of storing a plurality of bits, each bit stored in the mask register to control a respective one of the gates. 
 
 
   
   
     2. The apparatus of  claim 1 , wherein the logic circuit includes:
 an XOR (exclusive OR) gate having an output coupled to the shift register; and 
 an MXOR (multi-exclusive OR) gate having a plurality of inputs each coupled to the output of a respective one of the plurality of gates and an output coupled to an input of the XOR gate. 
 
   
   
     3. The apparatus of  claim 2 , wherein each of the plurality of gates is an AND gate having an input coupled to a respective bit of the mask register. 
   
   
     4. An apparatus comprising:
 an interface to be coupled to an item of telephony equipment; and 
 a de-scrambler coupled to the interface to receive from the interface an inbound signal to be de-scrambled, the de-scrambler including:
 a shift register having a plurality of taps, said shift register coupled to the interface to store bits of said inbound signal; 
 a logic circuit having a plurality of inputs and an output, one of said inputs of said logic circuit coupled to said interface to receive said inbound signal, said output of said logic circuit for outputting a de-scrambled inbound signal; 
 a plurality of gates each having a respective input coupled to one of the taps and a respective output coupled to a respective one of the inputs of the logic circuit; and 
 a mask register coupled to the plurality of gates and capable of storing a plurality of bits, each bit stored in the mask register to control a respective one of the gates. 
 
 
   
   
     5. The apparatus of  claim 4 , wherein the logic circuit includes:
 an XOR (exclusive OR) gate having a first input and a second input, the second input being coupled in common with an input of the shift register; and 
 an MXOR (multi-exclusive OR) gate having a plurality of inputs each coupled to the output of a respective one of the plurality of gates and an output coupled to the first input of the XOR gate. 
 
   
   
     6. The apparatus of  claim 5 , wherein each of the plurality of gates is an AND gate having an input coupled to a respective bit of the mask register. 
   
   
     7. An apparatus comprising:
 an interface to be coupled to an item of telephony equipment; 
 a scrambler coupled to the interface to provide an output signal to the interface; and 
 a de-scrambler coupled to the interface to receive an input signal; 
 wherein the scrambler includes:
 a first logic circuit having a plurality of inputs and an output; 
 a first shift register coupled to the output of the logic circuit and having a plurality of taps; 
 a first plurality of gates each having a respective input coupled to one of the taps of the first shift register and a respective output coupled to a respective one of the inputs of the first logic circuit; and 
 a mask register coupled to the first plurality of gates and capable of storing a plurality of bits, each bit stored in the mask register to control a respective one of the first plurality of gates; 
 
 and the de-scrambler includes:
 a second shift register separate from said first shift register and having a plurality of taps; 
 a second logic circuit separate from said first logic circuit and having a plurality of inputs and an output; and 
 a second plurality of gates separate from said first plurality of gates, each of said second plurality of gates having a respective input coupled to one of the taps of the second shift register and a respective output coupled to a respective one of the inputs of the second logic circuit; 
 
 the mask register also being coupled to the second plurality of gates and each bit stored in the mask register also being capable of controlling a respective one of the second plurality of gates. 
 
   
   
     8. The apparatus of  claim 7 , wherein each of the first plurality of gates is an AND gate having an input coupled to a respective bit of the mask register. 
   
   
     9. The apparatus of  claim 7 , wherein each of the second plurality of gates is an AND gate having an input coupled to a respective bit of the mask register.