Write circuit of memory device

Abstract

A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value.

1. A write circuit of a semiconductor memory device, comprising:
 a global data input/output (I/O) line; 
 an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and 
 a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value. 
 
   
   
     2. The write circuit as recited in  claim 1 , further comprising:
 a global latch block for latching the global data to prevent the global data I/O line from floating; 
 a prefetch block for receiving and prefetching input data transmitted via a data pad and outputting the input data as prefetched data during a write operation; and 
 a data transferring block for receiving the prefetched data and outputting the received data as the write data to the amplifying block in response to a column address and a burst type set by a mode register. 
 
   
   
     3. The write circuit as recited in  claim 1 , wherein the control block includes:
 a comparing block for comparing the write data with the global data; and 
 a signal generating block for generating an amplifying enable signal for controlling the amplifying block by combining a clock signal and an output of the comparing block. 
 
   
   
     4. The write circuit as recited in  claim 3 , wherein the comparing block is always enabled. 
   
   
     5. The write circuit as recited in  claim 4 , wherein the comparing block includes a first logic gate for performing exclusive OR operation of the write data and the global data and the signal generating block includes a second logic gate for performing an AND operation of the clock signal and the output of the comparing block to output the amplifying enable signal to the amplifying block. 
   
   
     6. The write circuit as recited in  claim 3 , wherein the comparing block is selectively enabled based on a comparison enable signal. 
   
   
     7. The write circuit as recited in  claim 6 , wherein the comparing block includes a first logic gate for performing an exclusive NOR operation of the write data and the global data and a second logic gate for performing an NAND operation of the comparison enable signal and an output of the first logic gate, and the signal generating block includes a third logic gate for performing an AND operation of the clock signal and an output of the second logic gate of the comparing block to output the AND operated signal as the amplifying enable signal to the amplifying block. 
   
   
     8. The write circuit as recited in  claim 7 , wherein the comparison enable signal is generated based on a test mode signal inputted from external. 
   
   
     9. The write circuit as recited in  claim 7 , wherein the comparison enable signal is generated by using a fuse option circuit. 
   
   
     10. The write circuit as recited in  claim 9 , wherein the fuse option circuit includes:
 a fuse option for transferring a first voltage to a first node; 
 an NMOS transistor for transferring a second voltage to the first node in response to an external power-up signal input; 
 a latch unit for latching one of logic values of the first voltage and the second voltage; and 
 an inverter for inverting an output of the latch unit and outputting the inverted signal as the comparison enable signal to the comparing block. 
 
   
   
     11. The write circuit as recited in  claim 7 , wherein the comparison enable signal is generated by a comparing control unit employing a fuse option and a test mode signal. 
   
   
     12. The write circuit as recited in  claim 11 , wherein the comparing control unit includes:
 a fuse option for transferring a first voltage to a first node; 
 an NMOS transistor for transferring a second voltage to the first node in response to a power-up signal inputted from external; 
 a latch unit for latching one of the logic values of the first voltage and the second voltage; 
 an inverter for inverting an output of the latch unit; and 
 a fourth logic gate for performing an OR operation of the test mode signal and an output of the inverter and outputting the OR operated signal as the comparison enable signal to the comparing block. 
 
   
   
     13. The write circuit as recited in  claim 3 , wherein the amplifying block includes:
 a differential amplifying block for sensing and amplifying the write data in response to the amplifying enable signal to output amplified differential signals; 
 an enable block for controlling the differential amplifying block in response to the amplifying enable signal; and 
 a driving block for driving the amplified differential signals and outputting the driven signal as the global data to the global data I/O line.