Reconfigurable filter node for an adaptive computing machine

Abstract

A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.

1. A reconfigurable filter node comprising:
 an input data memory adapted to store a plurality of input data values; 
 a filter coefficient memory adapted to store a plurality of filter coefficient values; and 
 a plurality of logically adjacent reconfigurable computational units adapted to simultaneously compute filter data values, wherein each computational unit is adapted to process at least one input data value and one filter coefficient; 
 wherein each computational unit comprises a first input data value register adapted to store an input data value, and at least one of the first input data value registers of the computational units is adapted to load a successive input data value from the first input data value register of a logically adjacent computational unit; and 
 each computational unit being configured to perform a filter convolution on the input data values using the filter coefficient provided by the filter coefficient memory, and each computation unit being adapted to receive a different one of the filter coefficients so that different ones of the reconfigurable computational units apply different functions to the input data values. 
 
   
   
     2. The reconfigurable filter node of  claim 1 , wherein the plurality of logically adjacent computational units comprises a left computational unit, a right computational unit, and a plurality of intermediate computational units logically positioned between the left and right computational units. 
   
   
     3. The reconfigurable filter node of  claim 2 , wherein all of the plurality of intermediate computational units are adapted to load a successive input data value from the first input data value register of a logically adjacent computational unit. 
   
   
     4. The reconfigurable filter node of  claim 3 , wherein each computational unit further comprises a second input data value register adapted to store an input data value. 
   
   
     5. The reconfigurable filter node of  claim 4 , wherein each second input data value register of the intermediate computational units is adapted to load a successive input data value from the second input data value register of an adjacent computational unit. 
   
   
     6. The reconfigurable filter node of  claim 5 , wherein the first and second input data value registers of each intermediate computational unit load successive data input values from different adjacent computational units. 
   
   
     7. The reconfigurable filter node of  claim 5 , wherein at least one multiplexer located between a pair of adjacent intermediate computational units selectively disengages the pair of adjacent first and second input data registers and selectively engages the pair of adjacent first and second data registers to the input data memory. 
   
   
     8. The reconfigurable filter node of  claim 1 , wherein the filter data values are the outputs of a filter in response to input data values. 
   
   
     9. The reconfigurable filter node of  claim 8 , wherein the filter is a real, single rate finite impulse response filter. 
   
   
     10. The reconfigurable filter node of  claim 9 , wherein the filter is asymmetric. 
   
   
     11. The reconfigurable filter node of  claim 9 , wherein the filter is symmetric. 
   
   
     12. The reconfigurable filter node of  claim 8 , wherein the filter is a half-complex, single rate finite impulse response filter. 
   
   
     13. The reconfigurable filter node of  claim 8 , wherein the filter is a polyphase finite impulse response filter. 
   
   
     14. The reconfigurable filter node of  claim 13 , wherein the filter is a decimation filter. 
   
   
     15. The reconfigurable filter node of  claim 13 , wherein the filter is an interpolation filter. 
   
   
     16. The reconfigurable filter node of  claim 13 , wherein the filter has at least one symmetrical sub-filter. 
   
   
     17. The reconfigurable filter node of  claim 8 , wherein the filter is an adaptive finite impulse response filter. 
   
   
     18. The reconfigurable filter node of  claim 8 , wherein the adjacent intermediate computational units are configured to enable shifting of data in either direction between the adjacent computational units. 
   
   
     19. The reconfigurable filter node of  claim 1 , wherein the filter data values are a second plurality of filter coefficients to be used in subsequent filter data value computations. 
   
   
     20. The reconfigurable filter node of  claim 1 , wherein the plurality of computational units is eight. 
   
   
     21. The reconfigurable filter node of  claim 1 , wherein the input data memory stores I (inphase) and Q (quadature) data for simultaneous filtering of separate I and Q signals. 
   
   
     22. A reconfigurable filter node comprising:
 an input data memory adapted to store a plurality of input data values; 
 a filter coefficient memory adapted to store a plurality of filter coefficient values; and 
 a plurality of logically adjacent reconfigurable computational units adapted to simultaneously compute filter data values, wherein each computational unit is adapted to process at least one input data value and one filter coefficient; 
 wherein each computational unit comprises a first input data value register adapted to store an input data value, and at least one of the first input data value registers of the computational units is adapted to load a successive input data value from the first input data value register of a logically adjacent computational unit; 
 each computational unit being configured to perform a filter convolution on the input data values using the filter coefficient provided by the filter coefficient memory, and 
 wherein the filter data values are a second plurality of filter coefficients to be used in subsequent filter data value computations. 
 
   
   
     23. The reconfigurable node of  claim 22 , wherein the filter values are stored in the filter coefficient memory. 
   
   
     24. The reconfigurable filter node of  claim 22 , wherein each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately a single input data value. 
   
   
     25. The reconfigurable filter node of  claim 24 , wherein each computational unit further comprises a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result. 
   
   
     26. The reconfigurable filter node of  claim 25 , wherein the coefficient memory selects a first filter coefficient for simultaneous use by a first plurality of computational units; and
 a multiplexer alternately selects either the first filter coefficient or a second filter coefficient from the coefficient memory for use by a second plurality of computational units. 
 
   
   
     27. The reconfigurable filter node of  claim 25 , further comprising an output data multiplexer for selectively accessing a filter data value from each of the plurality of computational units. 
   
   
     28. The reconfigurable filter node of  claim 27 , further comprising an output data memory for storing filter data values. 
   
   
     29. The reconfigurable filter node of  claim 28 , further comprising a data address generator for directing filter data values to specified memory addresses within the output data memory. 
   
   
     30. The reconfigurable filter node of  claim 28 , further comprising a data address generator for specifying memory addresses within the output data memory to retrieve filter data values. 
   
   
     31. A reconfigurable filter node comprising:
 an input data memory adapted to store a plurality of input data values; 
 a filter coefficient memory adapted to store a plurality of filter coefficient values; and 
 a plurality of logically adjacent reconfigurable computational units adapted to simultaneously compute filter data values, wherein each computational unit is adapted to process at least one input data value and one filter coefficient; 
 wherein each computational unit comprises a first input data value register adapted to store an input data value, and at least one of the first input data value registers of the computational units is adapted to load a successive input data value from the first input data value register of a logically adjacent computational unit; 
 including a multiplexer for selecting data from either an output of the computational unit or the input data memory to provide either partially or completely filtered data to an output; 
 each computational unit being configured to perform a filter convolution on the input data values using the filter coefficient provided by the filter coefficient memory, and each computation unit being adapted to receive a different one of the filter coefficients so that different ones of the reconfigurable computational units apply different functions to the input data values; and 
 wherein the input data memory stores I (inphase) and Q (quadature) data for simultaneous filtering of separate I and Q signals. 
 
   
   
     32. The reconfigurable filter node of  claim 31 , wherein the input data memory stores the I and Q data in a single word.