Method for processing a MEMS/CMOS cantilever based memory storage device

Abstract

A method is disclosed. The method includes fabricating microelectromechanical (MEMS) structures of a Seek and Scan Probe (SSP) memory device on a first wafer, and fabricating CMOS and memory medium components of the SSP memory device on a second wafer.

1. A method comprising:
 fabricating microelectromechanical (MEMS) structures of a Seek and Scan Probe (SSP) memory device on a first wafer; and 
 fabricating CMOS and memory medium components of the SSP memory device on a second wafer. 
 
     
     
       2. The method of  claim 1  further comprising bonding the first wafer and the second wafer. 
     
     
       3. The method of  claim 2  further comprising grinding the first wafer. 
     
     
       4. The method of  claim 3  further comprising etching the first Wafer to form a MEMS moving part. 
     
     
       5. The method of  claim 4  further comprising fabricating a cover wafer to enclose the MEMS moving part. 
     
     
       6. The method of  claim 5  further comprising bonding the cover wafer to the second wafer. 
     
     
       7. The method of  claim 1  wherein fabricating the first wafer comprises:
 depositing a first polysilicon layer over an oxide layer; and 
 layering silicon nitride over the first polysilicon layer. 
 
     
     
       8. The method of  claim 7  further comprising a process of defining cantilever beams on the first wafer, including:
 applying a lithography mask over the silicon nitride layer; 
 etching the silicon nitride and polysilicon layers; 
 depositing a second thin layer of oxide; 
 depositing a second polysilicon layer; and 
 depositing an oxide mask over the second polysilicon layer. 
 
     
     
       9. The method of claim S further comprising a process of forming the tip of the cantilever beams on the first wafer, including:
 depositing a second lithography mask over the oxide mask; 
 etching the polysilicon layer to form a sharp polysilicon tip under the oxide; 
 performing a poly anisotropic etch; and 
 performing a sharpening oxidation. 
 
     
     
       10. The method of  claim 9  further comprising a process of fanning one or more conductive traces on the first wafer, including:
 etching the oxide mask layer; 
 depositing a thin metal layer over the polysilicon layer; 
 performing a metal lithography process; and 
 performing a metal etch. 
 
     
     
       11. The method of  claim 10  Thither comprising a process of forming a thick metal on the first wafer, including:
 performing a resist coating and pattern process; 
 performing a metal seed sputter; 
 performing a mold e-plating process; 
 removing mold; 
 etching the seed; an 
 stripping the resist coat. 
 
     
     
       12. The method of  claim 11  further comprising a process of releasing the cantilever beams, including:
 forming trenches to initiate the release of the cantilever beams by performing an etch of portions of the silicon nitride layer; 
 etching exposed portions of the polysilicon layer 
 etching the exposed oxide layer; and 
 etching the silicon layer. 
 
     
     
       13. The method of  claim 12  flitter comprising etching the oxide layer underneath the polysilicon layer to release the cantilever.