Physical layers

Abstract

Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

1. A physical layer segment including a delay line generator comprising:
 A first bias generator, 
 And a second bias generator having: 
 a positive reference, 
 a negative reference, 
 a first bandgap reference, 
 and a second bandgap reference, 
 A voltage control input, 
 A delay line output, 
 A first MOSFET having a first doping,
 Conductively coupling said first reference to said delay line output, 
 And coupled at its gate to said voltage control input, 
 
 A second MOSFET having a first doping,
 Conductively coupling said first reference to said delay line output, 
 And coupled at its gate to said first bandgap reference, 
 
 A third MOSFET having a complementary doping to said first doping,
 Conductively coupling said second reference to said delay line output, And coupled at its gate to said second bandgap reference, 
 
 And a fourth MOSFET having a complementary doping to said first doping,
 Conductively coupling said second reference to said delay line output, 
 And coupled at its gate to said delay line output. 
 
 
   
   
     2. The physical layer segment according to  claim 1 , wherein the voltage control input is coupled to the first bias generator. 
   
   
     3. The physical layer segment according to  claim 1 , wherein one of the first and second bias generators are a positive bias generator, the other being a negative bias generator. 
   
   
     4. The physical layer segment according to  claim 3 , wherein the first bias generator is the complement of the second bias generator with respect to doping and reference biasing.