Methods and systems for implementing a Digital-to-Analog Converter

Abstract

A self-contained DAC that is especially suitable for use as an IP core, particularly for SOC (System on Chip) implementation. Techniques are applied to employ certain circuits (such as arithmetic element 302 ) to perform multiple functions in the DAC, thereby resulting in space saving. Techniques are also applied to employ fewer circuits per functional block to achieve further space saving. By employing multiple clock domains and turning on selective circuits on an as-needed basis, power saving is also realized.

1. A digital-to-analog converter (DAC) circuit for converting digital input data to analog data, comprising:
 an input host interface circuit configured to receive the digital input data; and 
 an interpolator circuit configured to interpolate at least a portion of the digital input data received by the input host interface circuit and to generate interpolated data, wherein the interpolator circuit is implemented with multiple interpolator stages sharing an arithmetic unit for computing the interpolated data, the multiple interpolator stages representing at least one of a cascade of four finite impulse response half-band filters and a cascade of digital filters and zero order holds, the digital filters having selectable kernel lengths and word widths. 
 
   
   
     2. The DAC circuit of  claim 1  wherein the digital filters are finite impulse response filters. 
   
   
     3. The DAC circuit of  claim 1  wherein the digital filters are infinite impulse response filters. 
   
   
     4. The DAC circuit of  claim 1  wherein the digital filters are Lagrangian interpolation filters. 
   
   
     5. The DAC circuit of  claim 1  wherein the digital filters represent cascaded integrator-comb filters. 
   
   
     6. The DAC circuit of  claim 1  wherein the multiple interpolator stages are implemented by a plurality of microprograms configured to be executed by the arithmetic unit. 
   
   
     7. The DAC circuit of  claim 6  further comprising a program counter circuit, wherein each of the plurality of microprograms is associated with a control field value, a microprogram of the plurality of microprograms is executed by the arithmetic unit when its associated control field value matches a program counter value provided by the program counter circuit. 
   
   
     8. The DAC circuit of  claim 1  further comprising:
 a volume control circuit configured to generate volume-weighted data from the interpolated data; and 
 a noise shaper circuit for reducing a word width of the volume-weighted data to generate reduced-width noise shaper output. 
 
   
   
     9. The DAC circuit of  claim 8  wherein the volume control circuit is implemented by explicit hardware multiplication using a multiplier and volume control data provided by a host. 
   
   
     10. The DAC circuit of  claim 8  wherein the volume control circuit is implemented by explicit hardware multiplication using a multiplier and volume control data provided by lookup table output from a lookup table, the lookup table receiving a volume control word and providing the volume control data to the multiplier. 
   
   
     11. The DAC circuit of  claim 10  wherein the digital input data is received as two separate data streams comprising a first data stream for left channel samples and a second data stream for right channel samples. 
   
   
     12. The DAC circuit of  claim 10  wherein the digital input data is received as single data stream wherein left channel sample data and right channel sample data are processed sequentially in different clock cycles in the interpolator circuit. 
   
   
     13. The DAC circuit of  claim 8  wherein the volume control circuit is implemented as the last stage of the interpolator circuit. 
   
   
     14. The DAC circuit of  claim 13  wherein interpolator coefficients of the last stage are integers {x,y,z}, the interpolator coefficients are provided by a structure that is one of a lookup table and a plurality of registers such that for a given volume setting v, the structure results in values {xv, yv, zv}. 
   
   
     15. A digital-to-analog converter (DAC) circuit for converting digital input data to analog data, comprising:
 an input host interface circuit configured to receive the digital input data; 
 an interpolator circuit configured to interpolate at least a portion of the digital input data that is received by the input host interface circuit and to generate interpolated data; 
 a volume control circuit configured to generate volume-weighted data from the interpolated data; and 
 a noise shaper circuit for reducing the word width of the volume-weighted data to generate reduced-width shaper output, 
 wherein the volume control circuit and the interpolator circuit share an arithmetic element to generate the interpolated data and to generate the volume weighted data. 
 
   
   
     16. The DAC circuit of  claim 15  wherein the volume control circuit is implemented by explicit hardware multiplication using a multiplier and volume control data provided by a host. 
   
   
     17. The DAC circuit of  claim 15  wherein the volume control circuit is implemented by explicit hardware multiplication using a multiplier and volume control data provided by lookup table output from a lookup table, the lookup table receiving a volume control word and providing the volume control data to the multiplier. 
   
   
     18. The DAC circuit of  claim 15  wherein the volume control circuit is implemented as the last stage of the interpolator circuit. 
   
   
     19. The DAC circuit of  claim 18  wherein interpolator coefficients of the last stage are integers {x,y,z}, the interpolator coefficients are provided by a structure that is one of a lookup table and a plurality of registers such that for a given volume setting v, the structure results in values {xv, yv, zv}. 
   
   
     20. A digital-to-analog converter (DAC) circuit for converting digital input data to analog data, comprising:
 an input host interface circuit configured to receive the digital input data; 
 an interpolator circuit; 
 a volume control circuit coupled to the interpolator circuit, the interpolator circuit and the volume control circuit being configured to receive the digital input data and to output volume-weighted and interpolated data; 
 a noise shaper circuit coupled to receive the volume-weighted and interpolated data to generate reduced-width shaper output; 
 a transition generator circuit configured to generate a transition signal; and 
 a pulse width modulator circuit configured to receive the reduced-width shaper output and to produce a first pulse code modulation signal from the reduced width shaper output when the DAC is operating in a first state, the pulse width modulator circuit configured to receive the transition signal to produce a second pulse code modulation signal from the transition signal when the DAC is operating in a second state, the second state being characteristic of at least one of a power-up condition and a power-down condition, the first state being characteristic of operating conditions other than the at least one of the power-up condition and the power-down condition. 
 
   
   
     21. The DAC circuit of  claim 20  wherein the transition signal is configured to produce a smooth transition in the second pulse code modulation signal during the at least one of the power-up condition and the power-down condition. 
   
   
     22. The DAC circuit of  claim 20  wherein the transition signal comprises a plurality of pulse code modulation values, the pulse code modulation values being generated by dedicated arithmetic hardware. 
   
   
     23. The DAC circuit of  claim 20  wherein the transition signal comprises a plurality of pulse code modulation values, the pulse code modulation values being generated by one of a linear counter and an accumulator. 
   
   
     24. The DAC circuit of  claim 20  wherein the transition signal comprises a plurality of pulse code modulation values, the pulse code modulation values being generated by dedicated arithmetic hardware that is configured to produce a solution for a second order difference equation. 
   
   
     25. The DAC circuit of  claim 20  wherein the transition signal comprises a plurality of pulse code modulation values, the pulse code modulation values being generated by dedicated arithmetic hardware that is configured to produce values in accordance with a function of 0.5[1+cos(arg)]. 
   
   
     26. A digital-to-analog converter (DAC) circuit for converting digital input data to analog data, comprising:
 an input host interface circuit configured to receive the digital input data; 
 an interpolator circuit; 
 a volume control circuit coupled to the interpolator circuit, the interpolator circuit and the volume control circuit being configured to receive the digital input data from the input host interface circuit and to output volume-weighted and interpolated data; 
 a noise shaper circuit coupled to receive the volume-weighted and interpolated data to generate reduced-width shaper output; 
 a pulse width modulator circuit configured to receive the reduced-width shaper output and to produce a first pulse code modulation signal from the reduced width shaper output; and 
 an analog output circuit including an output buffer and a low-pass filter for receiving the first pulse code modulation signal and outputting the analog data, wherein the input host interface circuit employs a first clock associated with a first clock domain, the interpolator circuit, the volume control circuit, and the noise shaper circuit, and at least a portion of the pulse width modulation circuit employ a second clock associated with a second clock domain, the second clock being asynchronous relative to the first clock. 
 
   
   
     27. The DAC circuit of  claim 26  further comprising a transition generator circuit configured to generate a transition signal for use by the pulse width modulator circuit to generate a second pulse code modulation signal during at least one of a power-up condition and a power-down condition, the transition generator circuit employs the second clock associated with the second clock domain. 
   
   
     28. The DAC circuit of  claim 26  wherein the analog output circuit employs a third clock associated with a third clock domain, the third clock being asynchronous with respect to the second clock and the first clock. 
   
   
     29. The DAC circuit of  claim 28  wherein the second clock domain and the third clock domain are bridged by a FIFO circuit, circuitries in the second clock domain is activated from an idle state to produce the first pulse code modulation signal from an idle state when data output by the circuitries in the second clock domain is required by circuitries in the third clock domain. 
   
   
     30. The DAC circuit of  claim 26  wherein the second clock domain and the first clock domain are bridged by a FIFO circuit, circuitries in the first clock domain is activated from an idle state to receive the digital input data when the digital input data is required by circuitries in the second clock domain. 
   
   
     31. The DAC circuit of  claim 30  wherein the input host interface circuit is coupled to receive data from a host using a FIFO such that data transmitted from the host to the input host interface circuit is free of gaps due to non-uniformly spaced pulse code modulation samples.