Digital routing switch matrix for digitized radio-frequency signals

Abstract

Routing and distribution of radio-frequency (RF) signals is commonly achieved in the analog domain. However, improved performance and simplified circuit architectures may be obtained by first digitizing the RF signal, and then carrying out all routing in the digital domain. A new generation of scalable digital switches has been developed, which routes both the data and clock signals together, this being necessary to maintain the integrity of the digitized RF signal. Given the extremely high switching speeds necessary for these applications (tens of GHz), this is implemented using Rapid-Single-Flux-Quantum (RSFQ) logic with superconducting integrated circuits. Such a digital switch matrix may be applied to either the receiver or transmitter components of an advanced multi-band, multi-channel digital transceiver system, and is compatible with routing of signals with different clock frequencies simultaneously within the same switch matrix.

1. A switching element comprising a data signal input and a clock signal input for selectively directing data from said data signal input to a data signal output depending upon the state of a reset/set flip flop and for directing a clock signal from said clock signal input to a clock signal output, in which the data signal moves in parallel with, and is resynchronized by, the clock signal. 
   
   
     2. A switching matrix comprising switching elements of  claim 1 , comprising:
 a. a first set of input signals, comprising a data signal and a clock signal, connected to respective inputs of both a first switching element and to a second switching element; 
 b. a second set of input signals, comprising a data signal and a clock signal, connected to respective inputs of both a third switching element and to a fourth switching element; wherein 
 c. outputs from the first and third switching elements are connected to a first set of outputs, comprising a data line and a clock line; and 
 d. outputs from the second and fourth switching elements are connected to a second set of ouputs, comprising a data line and a clock line; 
 e. wherein input signals from said first set of input signals and said second set of input signals can be selectively routed to either said first set of outputs or said second set of outputs depending on the state of a control signal. 
 
   
   
     3. A non-blocking switch comprising at least one switching matrix of  claim 2 , in which at least four switching matricies are interconnected to selectively interconnect four sets of input signals to four sets of output signals in a non-blocking manner. 
   
   
     4. The switching element of  claim 1  in which a data input comes from a low pass ADC modulator. 
   
   
     5. The switching element of  claim 4  in which the low pass ADC modulator is a Delta modulator. 
   
   
     6. The switching element of  claim 4  in which the low pass ADC modulator is a Delta-Sigma modulator. 
   
   
     7. The switching element of  claim 1  in which a data input comes from a band pass ADC modulator. 
   
   
     8. The switching element of  claim 7  in which the band pass ADC modulator is a Delta-Sigma modulator. 
   
   
     9. The switching matrix of  claim 2 , in which a data output goes to a digital signal processor. 
   
   
     10. The switching matrix of  claim 9  in which the digital signal processor is configured as a cross correlator. 
   
   
     11. The switching matrix of  claim 10  in which the cross correlator is a digital multiplier. 
   
   
     12. The switching matrix of  claim 10  in which the cross correlator utilizes a digital waveform generator. 
   
   
     13. The switching matrix of  claim 10  in which the cross correlator comprises a digital decimation filter. 
   
   
     14. The switching matrix of  claim 9  in which the digital signal processor is configured as an autocorrelator. 
   
   
     15. The switching matrix of  claim 2 , in which a data input to the switching matrix comes from a digital transmit waveform generator. 
   
   
     16. The switching matrix of  claim 2  in which the transmit waveform generator comprises a digital interpolation filter. 
   
   
     17. The switching matrix of  claim 2  in which the transmit waveform generator comprises a digital multiplier. 
   
   
     18. The switching matrix of  claim 2  configured to connect at least one output to a combiner. 
   
   
     19. The switching matrix of  claim 18  in which the combiner is connected to a Direct Digital Synthesizer or a Digital to Analog Converter. 
   
   
     20. The switching matrix of  claim 18  in which the Direct Digital Synthesizer or a Digital to Analog Converter is connected to an amplifier. 
   
   
     21. The switching matrix of  claim 18  in which the combiner is connected to a Direct Digital Synthesizer or a Digital to Analog Converter through a pre-distortion circuit. 
   
   
     22. The switching matrix of  claim 21  in which the predistortion circuit compensates for non-linearities in at least one of a power amplifier and a transmission medium. 
   
   
     23. The switching matrix of  claim 21  in which output of the Direct Digital Synthesizer or a Digital to Analog Converter is applied to an amplifier. 
   
   
     24. A superconducting switching element comprising a data signal input and a clock signal input for selectively directing data from said data signal input to a data signal output depending upon the state of an RSFQ reset/set flip flop and for directing a clock signal from said clock signal input to a clock signal output, in which the data signal moves in parallel with, and is resynchronized by, the clock signal. 
   
   
     25. A switching matrix comprising switching elements of  claim 24 , comprising:
 a. a first set of input signals, comprising a data signal and a clock signal, connected to respective inputs of both a first switching element and to a second switching element; 
 b. a second set of input signals, comprising a data signal and a clock signal, connected to respective inputs of both a third switching element and to a fourth switching element; wherein c. outputs from the first and third switching elements are connected to a first set of outputs, comprising a data line and a clock line; and 
 d. outputs from the second and fourth switching elements are connected to a second set of ouputs, comprising a data line and a clock line; 
 e. wherein input signals from said first set of input signals and said second set of input signals can be selectively routed to either said first set of outputs or said second set of outputs depending on the state of a control signal. 
 
   
   
     26. A non-blocking switch comprising at least one switching matrix of  claim 25 , in which at least four switching matricies are interconnected to selectively interconnect four sets of input signals to four sets of output signals in a non-blocking manner. 
   
   
     27. The switching element of  claim 24  in which a data input comes from a low pass ADC modulator. 
   
   
     28. The switching element of  claim 27  in which the low pass ADC modulator is a Delta modulator. 
   
   
     29. The switching element of  claim 27  in which the low pass ADC modulator is a Delta-Sigma modulator. 
   
   
     30. The switching element of  claim 24  in which a data input comes from a band pass ADC modulator. 
   
   
     31. The switching element of  claim 30  in which the band pass ADC modulator is a Delta-Sigma modulator. 
   
   
     32. The switching matrix of  claim 25 , in which a data output goes to a digital signal processor. 
   
   
     33. The switching matrix of  claim 32  in which the digital signal processor is configured as a cross correlator. 
   
   
     34. The switching matrix of  claim 33  in which the cross correlator is a digital multiplier. 
   
   
     35. The switching matrix of  claim 33  in which the cross correlator utilizes a digital waveform generator. 
   
   
     36. The switching matrix of  claim 33  in which the cross correlator comprises a digital decimation filter. 
   
   
     37. The switching matrix of  claim 32  in which the digital signal processor is configured as an autocorrelator. 
   
   
     38. The switching matrix of  claim 25 , in which a data input to the switching matrix comes from a digital transmit waveform generator. 
   
   
     39. The switching matrix of  claim 25  in which the transmit waveform generator comprises a digital interpolation filter. 
   
   
     40. The switching matrix of  claim 25  in which the transmit waveform generator comprises a digital multiplier. 
   
   
     41. The switching matrix of  claim 25  configured to connect at least one output to a combiner. 
   
   
     42. The switching matrix of  claim 41  in which the combiner is connected to a Direct Digital Synthesizer or a Digital to Analog Converter. 
   
   
     43. The switching matrix of  claim 41  in which the Direct Digital Synthesizer or a Digital to Analog Converter is connected to an amplifier. 
   
   
     44. The switching matrix of  claim 41  in which the combiner is connected to a Direct Digital Synthesizer or a Digital to Analog Converter through a pre-distortion circuit. 
   
   
     45. The switching matrix of  claim 44  in which the predistortion circuit compensates for non-linearities in at least one of a power amplifier and a transmission medium. 
   
   
     46. The switching matrix of  claim 44  in which output of the Direct Digital Synthesizer or a Digital to Analog Converter is applied to an amplifier. 
   
   
     47. The switching element of  claim 1  in which the data signal input and the data signal output each comprise a respective plurality of binary data lines, with signals from each input binary data line being selectively directed to a corresponding output binary data line depending upon the state of said set/reset flip flop. 
   
   
     48. The switching element of  claim 24  in which the data signal input and the data signal output each comprise a respective plurality of binary data lines, with signals from each input binary data line being selectively directed to a corresponding output binary data line depending upon the state of said set/reset flip flop.