P
US7372385B2ActiveUtilityPatentIndex 63

A/D converter, signal processor, and receiving device

Assignee: TOSHIBA KKPriority: Jun 28, 2006Filed: Dec 20, 2006Granted: May 13, 2008
Est. expiryJun 28, 2026(expired)· nominal 20-yr term from priority
Inventors:YAMAJI TAKAFUMI
H03M 3/422H03M 3/464H03M 3/354H03M 3/41
63
PatentIndex Score
4
Cited by
16
References
20
Claims

Abstract

An A/D converter which converts an analog current signal into a digital signal, includes: a filter removing a noise component from the analog current signal to output an analog voltage signal; a quantizer quantizing the analog voltage signal outputted from the filter to generate the digital signal; and a D/A converter converting the digital signal generated by the quantizer into an analog feedback current to feedback to an input of the filter, and supplying a bias current for the D/A converter to an output of a frequency converter via a path of the analog current signal as a bias current driving the frequency converter outputting the analog current signal.

Claims

exact text as granted — not AI-modified
1. An A/D converter which converts an analog current signal into a digital signal, comprising:
 a filter removing a noise component from the analog current signal to output an analog voltage signal; 
 a quantizer quantizing the analog voltage signal outputted from said filter to generate the digital signal; and 
 a D/A converter converting the digital signal generated by said quantizer into an analog feedback current to feedback to an input of said filter, and supplying a bias current for said D/A converter to an output of a frequency converter via a path of the analog current signal as a bias current driving the frequency converter outputting the analog current signal. 
 
     
     
       2. The A/D converter according to  claim 1 ,
 wherein the bias current of said D/A converter flows from a positive power supply terminal of said D/A converter to an output terminal of said D/A converter. 
 
     
     
       3. The A/D converter according to  claim 1 , further comprising:
 a dynamic element matching processor converting the digital signal generated by said quantizer to make a noise component caused by an error of said D/A converter distributed at a attenuation region of said filter and inputting the digital signal to said D/A converter. 
 
     
     
       4. The A/D converter according to  claim 1 , further comprising:
 a common mode feedback circuit detecting a common mode component of output voltages of said D/A converter and the frequency converter, and controlling the bias current thereof to make the common mode component become a predetermined voltage. 
 
     
     
       5. The A/D converter according to  claim 1 ,
 wherein said D/A converter includes a pair of first MOSFETs in which gates thereof are connected to an output of said quantizer and drains thereof are connected to the input of said filter, and a second MOSFET in which a drain thereof is connected to sources of the first MOSFETs and a source thereof is connected to a reference potential. 
 
     
     
       6. The A/D converter according to  claim 1 ,
 wherein said quantizer generates the digital signal with the number of bits of two or more, and 
 wherein said D/A converter converts the digital signal with the number of bits corresponding to the number of bits of the digital signal outputted by said quantizer into the analog feedback current. 
 
     
     
       7. A signal processor, comprising:
 a frequency converter frequency converting an analog input signal to output an analog current signal; 
 a filter removing a noise component form the analog current signal to output an analog voltage signal; 
 a quantizer quantizing the analog voltage signal outputted from said filter to generate a digital output signal; and 
 a D/A converter converting the digital output signal generated by said quantizer into an analog feedback current to feedback to an input of said filter, and supplying a bias current for said D/A converter to an output of said frequency converter via a path of the analog current signal as a bias current driving said frequency converter. 
 
     
     
       8. The signal processor according to  claim 7 ,
 wherein the bias current of said D/A converter flows from a positive power supply terminal of said D/A converter to a negative power supply terminal of said frequency converter via an output terminal of said D/A converter and an output terminal of said frequency converter. 
 
     
     
       9. The signal processor according to  claim 7 , further comprising:
 a dynamic element matching processor converting the digital output signal generated by said quantizer to make a noise component caused by an error of said D/A converter distributed at a attenuation region of said filter and inputting the digital output signal to said D/A converter. 
 
     
     
       10. The signal processor according to  claim 7 , further comprising:
 a common mode feedback circuit detecting a common mode component of output voltages of said D/A converter and said frequency converter, and controlling the bias current thereof to make the common mode component become a predetermined voltage. 
 
     
     
       11. The signal processor according to  claim 7 ,
 wherein said D/A converter includes a pair of first MOSFETs in which gates thereof are connected to an output of said quantizer and drains thereof are connected to the input of said filter, and a second MOSFET in which a drain thereof is connected to sources of the first MOSFETs and a source thereof is connected to a first reference potential, and 
 wherein said frequency converter includes:
 a third MOSFET in which a source thereof is connected to a second reference potential different from the first reference potential, and the analog input signal is inputted to a gate thereof; and 
 a pair of fourth MOSFETs in which sources thereof are connected to a drain of the third MOSFET, a signal to perform the frequency conversion is inputted to gates thereof, and drains thereof are connected to the input of said filter. 
 
 
     
     
       12. The signal processor according to  claim 7 ,
 wherein said quantizer generates the digital output signal with the number of bits of two or more, and 
 wherein said D/A converter converts the digital output signal with the number of bits corresponding to the number of bits of the digital output signal outputted by said quantizer into the analog feedback current. 
 
     
     
       13. A signal processor, comprising:
 a frequency converter frequency converting an analog input signal to output an analog current signal; 
 a filter removing a noise component from the analog current signal to output an analog voltage signal; 
 a quantizer quantizing the analog voltage signal outputted from said filter to generate a digital output signal; and 
 a D/A converter converting the digital output signal generated by said quantizer into an analog feedback current to feedback to an input of said filter, and 
 wherein said frequency converter is driven by reusing a bias current of said D/A converter. 
 
     
     
       14. The signal processor according to  claim 13 ,
 wherein the bias current of said D/A converter flows from a positive power supply terminal of said D/A converter to a negative power supply terminal of said frequency converter via an output terminal of said D/A converter and an output terminal of said frequency converter. 
 
     
     
       15. The signal processor according to  claim 13 , further comprising:
 a dynamic element matching processor converting the digital output signal generated by said quantizer to make the noise component caused by an error of said D/A converter distributed at an attenuation region of said filter, and inputting the digital output signal to said D/A converter. 
 
     
     
       16. The signal processor according to  claim 13 , further comprising:
 a common mode feedback circuit detecting a common mode component of output voltages of said D/A converter and said frequency converter, and controlling the bias current thereof to make the common mode component become a predetermined voltage. 
 
     
     
       17. The signal processor according to  claim 13 ,
 wherein said D/A converter includes a pair of first MOSFETs in which gates thereof are connected to an output of said quantizer and drains thereof are connected to the input of said filter, and a second MOSFET in which a drain thereof is connected to sources of the first MOSFETs and a source thereof is connected to a first reference potential, and 
 wherein said frequency converter includes:
 a third MOSFET in which a source thereof is connected to a second reference potential different from the first reference potential, and the analog input signal is inputted to a gate thereof, and 
 a pair of fourth MOSFETs in which sources thereof are connected to a drain of the third MOSFET, a signal to perform the frequency conversion is inputted to gates thereof, and drains thereof are connected to the input of said filter. 
 
 
     
     
       18. The signal processor according to  claim 13 ,
 wherein said quantizer generates the digital output signal with the number of bits of two or more, and 
 wherein said D/A converter converts the digital output signal with the number of bits corresponding to the number of bits of the digital output signal outputted by said quantizer into the analog feedback current. 
 
     
     
       19. A receiving device, comprising:
 an amplifier amplifying a received signal; 
 a signal processor according to  claim 7 ; and 
 a digital processor decrypting a digital output signal. 
 
     
     
       20. A receiving device, comprising:
 an amplifier amplifying a received signal; 
 a signal processor according to  claim 13 ; and 
 a digital processor decrypting a digital output signal.

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