Generation of graphical design representation from a design specification data file

Abstract

Method and apparatus are described for generating a block diagram of an electronic circuit design. In one embodiment, each instance of a multi-master bus, a bus master of a multi-master bus, a bus slave of a multi-master bus, a memory, a co-processor and an input/output port is are identified. Instances of input/output ports are placed about a perimeter of a first area of the diagram. Each instance of a multi-master bus is placed in a bus area within the first area and each bus master is placed in a master area. The bus slaves of a bus are collected in a group, and the group is placed as a single block in a slave area within the first area. The group of bus slave slaves is aligned with a bus master. A diagrammatic representation is output consistent with the placement representations.

1. A processor-implemented method for generating a block diagram of an electronic circuit design, comprising:
 identifying by a processor from an input textual description of the electronic circuit design, each multi-master bus, bus master of a multi-master bus, bus slave of a multi-master bus, memory, co-processor and input/output port; 
 representing in a memory coupled to the processor, diagrammatic placement of each input/output port about a perimeter of a first area; 
 representing in the memory, a bus area, a master area, and a slave area within the first area; 
 representing in the memory, placement in the bus area of each multi-master bus; 
 representing in the memory, placement in the master area of each bus master, wherein no bus master is placed between another bus master and a multi-master bus; 
 representing in the memory, a group of bus slaves of a multi-master bus, wherein each bus slave in the group has a slave connection to the multi-master bus and no other connection to any bus master of the multi-master bus; 
 representing in the memory, placement of the group of bus slaves as a single block in the bus area, wherein the group is diagrammatically aligned with a bus master of the multi-master bus to which the group of bus slaves is connected; 
 representing in the memory, connections between each multi-master bus and each bus master of the multi-master bus and a connection between the multi-master bus and the group of bus slaves with respective connection lines; and 
 outputting a diagrammatic representation consistent with the representations of the placement of each identified multi-master bus, bus master, bus slave, and connections. 
 
   
   
     2. The method of  claim 1 , wherein the bus area is between the master area and the slave area. 
   
   
     3. The method of  claim 2 , wherein the master area is above the bus area. 
   
   
     4. The method of  claim 2 , further comprising:
 identifying by the processor from the input textual description of the electronic circuit design, each memory block and each co-processor; 
 associating with each bus master that specifies a processor, each memory block that is local to the bus master and each co-processor of the processor; and 
 representing in the memory, placement of each memory block and each co-processor that is associated with a bus master, wherein the placement of the memory block and the co-processor is aligned with the associated bus master. 
 
   
   
     5. The method of  claim 4 , wherein for placement of each memory block and each co-processor that is associated with a bus master, the bus master is between the bus area and the memory block and the co-processor. 
   
   
     6. The method of  claim 5 , wherein placement of each memory block that is associated with a bus master is above placement of the bus master in the master area. 
   
   
     7. The method of  claim 6 , wherein placement of each co-processor associated with the bus master is above placement of each memory block associated with the bus master. 
   
   
     8. The method of  claim 5 , further comprising:
 determining for each bus master, a respective total number of associated memory blocks and co-processors; and 
 determining placement of identified bus masters in order from a bus master with a greatest number of associated memory blocks and co-processors to a bus master with a least number of associated memory blocks and co-processors. 
 
   
   
     9. The method of  claim 6 , wherein placement of the bus master with the greatest number of associated memory blocks and co-processors is centered in the master area. 
   
   
     10. The method of  claim 1 , further comprising:
 identifying by the processor from an input textual description of the electronic circuit design, each bridge between a pair of multi-master buses; 
 representing in the memory, placement in the bus area of each bridge; and 
 representing in the memory, connections between each bridge and the pair of multi-master buses with connection lines; and 
 wherein the outputting of the diagrammatic representation includes each bridge and the connections between the bridge to the pair of multi-master buses. 
 
   
   
     11. The method of  claim 10 , wherein placement of each bridge is directly below one multi-master bus of the pair of multi-master buses to which the bridge has a slave connection. 
   
   
     12. The method of  claim 10 , further comprising:
 identifying by the processor from an input textual description of the electronic circuit design, each miscellaneous design block having no connections to any multi-master bus; 
 representing in the memory, placement in the slave area of each miscellaneous design block as a single block including each miscellaneous design block without connection lines; and 
 wherein the outputting of the diagrammatic representation includes the single block including each miscellaneous design block. 
 
   
   
     13. The method of  claim 12 , wherein placement of the single block is below each group of bus slaves. 
   
   
     14. The method of  claim 12 , wherein the bus area is between the master area and the slave area. 
   
   
     15. The method of  claim 14 , further comprising:
 identifying by the processor from the input textual description of the electronic circuit design, each memory block and each co-processor; 
 associating with each bus master that specifies a processor, each memory block that is local to the bus master and each co-processor of the processor; and 
 representing in the memory, placement of each memory block and each co-processor that is associated with the bus master, wherein the placement of the memory block and the co-processor is aligned with the associated bus master. 
 
   
   
     16. The method of  claim 15 , further comprising:
 determining for each bus master, a respective total number of associated memory blocks and co-processors; and 
 determining placement of identified bus masters in order from a bus master with a greatest number of associated memory blocks and co-processors to a bus master with a least number of associated memory blocks and co-processors. 
 
   
   
     17. The method of  claim 16 , wherein placement of the bus master with the greatest number of associated memory blocks and co-processors is centered in the master area. 
   
   
     18. The method of  claim 17 , wherein placement of each memory block that is associated with a bus master is above placement of the bus master in the master area, and placement of each co-processor associated with the bus master is above placement of each memory block associated with the bus master. 
   
   
     19. An apparatus for generating a block diagram of an electronic circuit design, comprising:
 means for identifying from an input textual description of the electronic circuit design, each multi-master bus, bus master of a multi-master bus, bus slave of a multi-master bus, and input/output port; 
 means for representing diagrammatic placement of each input/output port about a perimeter of a first area; 
 means for representing a bus area, a master area, and a slave area within the first area; 
 means for representing in the memory, placement in the bus area of each multi-master bus; 
 means for representing placement in the master area of each bus master of a multi-master bus, wherein no bus master is placed between another bus master and a multi-master bus; 
 means for representing a group of bus slaves of a multi-master bus, wherein each bus slave in the group has a slave connection to the multi-master bus and no other connection to any bus master of the multi-master bus; 
 means for representing placement of the group of bus slaves as a single block in the bus area, wherein the group is diagrammatically aligned with a bus master of the multi-master bus to which the group of bus slaves is connected; 
 means for representing connections between each multi-master bus and each bus master of the multi-master bus and a connection between the multi-master bus and the group of bus slaves with connection lines; and 
 means for outputting a diagrammatic representation consistent with the representations of the placement of each identified multi-master bus, bus master, bus slave, and connections. 
 
   
   
     20. An article of manufacture, comprising:
 a processor-readable medium configured with instructions executable by a processor for generating a block diagram of an electronic circuit design by performing steps including,
 identifying by the processor from an input textual description of the electronic circuit design, each multi-master bus, bus master of a multi-master bus, bus slave of a multi-master bus, and input/output port; 
 representing in a memory coupled to the processor, diagrammatic placement of each input/output port about a perimeter of a first area; 
 representing in the memory, a bus area, a master area, and a slave area within the first area; 
 representing in the memory, placement in the bus area of each multi-master bus; 
 representing in the memory, placement in the master area of each bus master of a multi-master bus, wherein no bus master is placed between another bus master and a multi-master bus; 
 representing in the memory, a group of bus slaves of a multi-master bus, wherein each bus slave in the group has a slave connection to the multi-master bus and no other connection to any bus master of the multi-master bus; 
 representing in the memory, placement of the group of bus slaves as a single block in the bus area, wherein the group is diagrammatically aligned with a bus master of the multi-master bus to which the group of bus slaves is connected; 
 representing in the memory, connections between each multi-master bus and each bus master of the multi-master bus and a connection between the multi-master bus and the group of bus slaves with respective connection lines; and 
 outputting a diagrammatic representation consistent with the representations of the placement of each identified multi-master bus, bus master, bus slave, and connections.