CMOS buffer with complementary outputs having reduced voltage swing

Abstract

A buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels includes first and second branches outputting first and second complementary output signals, respectively. Each branch includes a PMOS and an NMOS transistor connected in series with a voltage-swing adjusting transistor between a first supply voltage and a second supply voltage. Control terminals of the PMOS and NMOS transistors each receive one of the complementary input signals, and a control terminal of the first voltage-swing adjusting transistor receives a first bias voltage. When the complementary input signal has a first voltage level, the voltage-swing adjusting transistor operates in a linear region and when the first complementary input signal has a second voltage level, current through the voltage-swing adjusting transistor is shut-off. No current flows in either branch when the buffer is in a static state.

1. A buffer for interfacing complementary input signals having complementary metal oxide semiconductor (CMOS) voltage levels to a circuit operating with current mode logic (CML) voltage levels, the buffer comprising:
 a first branch receiving a first one of the complementary input signals and outputting a first complementary output signal having CML voltage levels, the first branch including,
 a first PMOS transistor having a first terminal connected to a first CMOS supply voltage, a second terminal providing the first complementary output signal, and a control terminal receiving the first complementary input signal, and 
 a first NMOS transistor and a second PMOS transistor connected in series between the second terminal of the first PMOS transistor and a second CMOS supply voltage, the first NMOS transistor having a control terminal receiving the first complementary input signal, and the second PMOS transistor having a control terminal receiving a first branch bias voltage; 
 
 a second branch receiving a second one of the complementary input signals and outputting a second complementary output signal having CML voltage levels, the second branch including,
 a third PMOS transistor having a first terminal connected to the first CMOS supply voltage, a second terminal providing the second complementary output signal, a control terminal receiving the second complementary input signal, and 
 a second NMOS transistor and a fourth PMOS transistor connected in series between the second terminal of the third PMOS transistor and the second CMOS supply voltage, the second NMOS transistor having a control terminal receiving the second complementary input signal, and the fourth PMOS transistor having a control terminal receiving a second branch bias voltage. 
 
 
   
   
     2. The buffer of  claim 1 , wherein:
 the first NMOS transistor has a first terminal connected to the second CMOS supply voltage, and a second terminal; and 
 the second PMOS transistor has a first terminal connected to the second terminal of the first NMOS transistor, and a second terminal connected to the second terminal of the first NMOS transistor. 
 
   
   
     3. The buffer of  claim 2 , wherein:
 the second NMOS transistor has a first terminal connected to the second CMOS supply voltage, and a second terminal; and 
 the fourth PMOS transistor has a first terminal connected to a second terminal of the third PMOS transistor, and a second terminal connected to the second terminal of the second NMOS transistor. 
 
   
   
     4. The buffer of  claim 1 , wherein:
 the second PMOS transistor has a first terminal connected to the second CMOS supply voltage, and a second terminal; 
 the first NMOS transistor has a first terminal connected to the second terminal of the first PMOS transistor, and a second terminal connected to the second terminal of the second PMOS transistor. 
 
   
   
     5. The buffer of  claim 4 , wherein:
 the fourth PMOS transistor has a first terminal connected to the second CMOS supply voltage, and a second terminal; and 
 the second NMOS transistor has a first terminal connected to a second terminal of the third PMOS transistor, and a second terminal connected to the second terminal of the fourth PMOS transistor. 
 
   
   
     6. The buffer of  claim 1 , further comprising:
 a first resistor connected between the control terminal of the second PMOS transistor and a voltage-swing-adjusting bias voltage; and 
 a second resistor connected between the control terminal of the fourth PMOS transistor and the voltage-swing-adjusting bias voltage. 
 
   
   
     7. The buffer of  claim 6 , wherein a resistance of the first resistor is the same as that of the second resistor. 
   
   
     8. The buffer of  claim 6 , wherein the first and second complementary output signals swing between an upper voltage that is about equal to t the first CMOS supply voltage, and a lower voltage that is about equal to a sum of the voltage-swing-adjusting bias voltage and a threshold voltage of one of the second and fourth PMOS transistors. 
   
   
     9. The buffer of  claim 1 , further comprising:
 a first capacitor connected between the control terminal of the second PMOS transistor and the second complementary input signal; and 
 a second capacitor connected between the control terminal of the fourth PMOS transistor and the first complementary input signal, 
 wherein the first and second capacitors have a same capacitance as each other. 
 
   
   
     10. A buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels, the buffer comprising:
 a first branch outputting a first complementary output signal from a first complementary output terminal, the first branch comprising a first NMOS transistor and a first voltage-swing-adjusting transistor connected in series with a first PMOS transistor between a first supply voltage and a second supply voltage, wherein the first NMOS transistor and first voltage-swing-adjusting transistor are further connected in series between the first complementary output terminal and the second supply voltage, wherein control terminals of the first PMOS and NMOS transistors of the first branch each receive a first one of the complementary input signals, and a control terminal of the first voltage-swing-adjusting transistor receives a first bias voltage, and wherein when the first complementary input signal has a first voltage level, the first voltage-swing-adjusting transistor operates in a linear region and when the first complementary input signal has a second voltage level, current through the first voltage-swing-adjusting transistor is shut-off by one of the first PMOS and NMOS transistors of the first branch; and 
 a second branch outputting a second complementary output signal from a second complementary output terminal, the second branch comprising a second NMOS transistor and a second voltage-swing-adjusting transistor connected in series with a second PMOS transistor between a first supply voltage and a second supply voltage, wherein the second NMOS transistor and second voltage-swing-adjusting transistor are further connected in series between the second complementary output terminal and the second supply voltage, wherein control terminals of the second PMOS and second NMOS transistors of the second branch each receive a second one of the complementary input signals, and a control terminal of the second voltage-swing-adjusting transistor receives a second bias voltage, and wherein when the second complementary input signal has a first voltage level, the second voltage-swing-adjusting transistor operates in a linear region and when the second complementary input signal has a second voltage level, current through the second voltage-swing-adjusting transistor is shut-off by one of the second PMOS and second NMOS transistors of the second branch; 
 a first resistor connected between the control terminal of the first voltage-swing transistor and a voltage-swing-adjusting bias voltage; and 
 a second resistor connected between the control terminal of the second voltage-swing transistor and the voltage-swing-adjusting bias voltage. 
 
   
   
     11. The buffer of  claim 10 , wherein a resistance of the first resistor is the same as that of the second resistor. 
   
   
     12. The buffer of  claim 10 , wherein the first and second complementary output signals swing between an upper voltage that is about equal to the first CMOS supply voltage, and a lower voltage that is about equal to a sum of the first voltage-swing-adjusting bias voltage and a threshold voltage of one of the first and second voltage-swing adjusting transistors. 
   
   
     13. A buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels, the buffer comprising:
 a first branch outputting a first complementary output signal from a first complementary output terminal, the first branch comprising a first NMOS transistor and a first voltage-swing-adjusting transistor connected in series with a first PMOS transistor between a first supply voltage and a second supply voltage, wherein the first NMOS transistor and first voltage-swing-adjusting transistor are further connected in series between the first complementary output terminal and the second supply voltage, wherein control terminals of the first PMOS and NMOS transistors of the first branch each receive a first one of the complementary input signals, and a control terminal of the first voltage-swing-adjusting transistor receives a first bias voltage, and wherein when the first complementary input signal has a first voltage level, the first voltage-swing-adjusting transistor operates in a linear region and when the first complementary input signal has a second voltage level, current through the first voltage-swing-adjusting transistor is shut-off by one of the first PMOS and NMOS transistors of the first branch; 
 a second branch outputting a second complementary output signal from a second complementary output terminal, the second branch comprising a second NMOS transistor and a second voltage-swing-adjusting transistor connected in series with a second PMOS transistor between a first supply voltage and a second supply voltage, wherein the second NMOS transistor and second voltage-swing-adjusting transistor are further connected in series between the second complementary output terminal and the second supply voltage, wherein control terminals of the second PMOS and second NMOS transistors of the second branch each receive a second one of the complementary input signals, and a control terminal of the second voltage-swing-adjusting transistor receives a second bias voltage, and wherein when the second complementary input signal has a first voltage level, the second voltage-swing-adjusting transistor operates in a linear region and when the second complementary input signal has a second voltage level, current through the second voltage-swing-adjusting transistor is shut-off by one of the second PMOS and second NMOS transistors of the second branch; 
 a first capacitor connected between the control terminal of the first voltage-swing adjusting transistor and the second complementary input signal; and 
 a second capacitor connected between the control terminal of the second voltage-swing adjusting transistor and the first complementary input signal, 
 wherein the first and second capacitors have a same capacitance as each other.