Delta-sigma AD converter

Abstract

The output of a first integrator is quantized in a quantizer. The quantized signal is subjected to D/A conversion, successively output to a plurality of output paths by a first switching circuit, sampled and held by a plurality of charge-holding circuits of a first feedback circuit, and successively output by a second switching circuit to one of the input terminals of a subtractor. On the other hand, the output signal of the first integrator is successively output by a third switching circuit to a plurality of output paths, sampled and held by a plurality of charge-holding circuits of a second feedback circuit, and successively input to the other input terminal of the subtractor by a fourth switching circuit along with signals held in an input portion, which samples and holds input analog signals. By doing so, a plurality of signals with different sampling timings are integrated accumulatively by the subtractor and the first integrator. When integration functions used to obtain an n-th order noise-shaping effect are multiplexed and operated using a single integrator, the integrator's current consumption can be suppressed.

1. A Delta-Sigma AD converter comprising:
 a subtractor outputting a difference of two analog input signals; 
 a first integrator integrating the output of the subtractor; 
 a quantizer quantizing the output signal of the first integrator; 
 a digital-to-analog converter outputting an analog signal in proportion to the output signal of the quantizer; 
 a first switching circuit that, for each predetermined sampling timing, switches the output signal of the digital-to-analog converter and successively outputs the output signal to different output paths; 
 a first feedback circuit having a plurality of charge-holding circuits respectively connected to different output paths from the first switching circuit, with the charge-holding circuits holding respectively differing amounts of feedback of a signal in proportion to the magnitude of the output signal of the digital-to-analog converter during predetermined sampling time intervals; 
 a second switching circuit that, for each sampling timing, switches the signal held in the first feedback circuit and outputs the signal to one of the input terminals of the subtractor, 
 an input portion that, for each predetermined sampling timing, holds a signal in proportion to the analog input signal during a fixed sampling time interval; 
 a third switching circuit that, for each predetermined sampling timing, switches the output signal of the first integrator and successively outputs the output signal to different output paths; 
 a second feedback circuit having a plurality of charge-holding circuits respectively connected to different output paths from the third switching circuit, with the charge-holding circuits holding differing amounts of feedback of a signal in proportion to the magnitude of the output signal of the first integrator input from the third switching circuit during predetermined sampling time intervals; and 
 a fourth switching circuit that, for each sampling timing, switches a signal held in the input portion and a signal held in the second feedback circuit and inputs the signal to the other input terminal of the subtractor; 
 wherein the plurality of signals of different sampling timings held in the first and second feedback circuits are integrated accumulatively in the subtractor and first integrator. 
 
     
     
       2. The Delta-Sigma AD converter according to  claim 1  comprising a second integrator that is inserted between the input portion and the fourth switching circuit, integrates signals held in the input portion, and inputs the signals to the input terminal of the fourth switching circuit. 
     
     
       3. The Delta-Sigma AD converter according to  claim 2 , wherein the input portion and second integrator are controlled using a sampling timing configured with a clock duty ratio different from the predetermined sampling time intervals in the first and second feedback circuits. 
     
     
       4. The delta-sigma AD converter according to  claim 1 , wherein the first and second feedback circuits are formed of switched capacitors. 
     
     
       5. The delta-sigma AD converter according to  claim 1 , wherein the first integrator is formed of two integrators and one feedback circuit. 
     
     
       6. The delta-sigma AD converter according to  claim 1 , comprising a filter order switching control portion connected so as to control the operation of the first to fourth switching circuits,
 wherein the characteristics of the first integrator, including the filter order, can be made variable by selectively switching the timing of operation and the paths of the charge-holding circuits being used based on control signals from the filter order switching control portion. 
 
     
     
       7. The delta-sigma AD converter according to  claim 1 , wherein the clocks controlling the sampling time intervals based on the first to fourth switching circuits are formed using a plurality of various clocks with different clock duty ratios. 
     
     
       8. The delta-sigma AD converter according to  claim 7 , wherein the clocks with different clock duty ratios are generated by frequency division from a single base clock. 
     
     
       9. The delta-sigma AD converter according to  claim 7 , wherein electric current supplied to the first integrator is switched in synchronism with the sampling timing.