System having interfaces, switch, and memory bridge for CC-NUMA operation

Abstract

A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.

1. An apparatus comprising:
 one or more coherent agents within a node coupled to an internal interconnect, in which the interconnect supports intranode coherency for transactions within the node with the one or more coherent agents; 
 a plurality of interface circuits coupled to communicate coherency commands between the interface circuits and respective remote nodes of a plurality of remote nodes; 
 a memory bridge coupled to the interconnect to maintain internode coherency for transactions between one or more coherent agents and the remote nodes, and to generate additional coherency commands responsive to coherent transactions on the interconnect, the memory bridge including an address map to map a node number associating a remote node with one of the interface circuits for communication of a respective coherency command from the memory bridge, via the associated interface circuit, to the remote node; and 
 a switch coupled to the interface circuits and the memory bridge to selectively couple the associated interface circuit to the memory bridge for transfer of the respective coherency command. 
 
   
   
     2. The apparatus of  claim 1  wherein each coherency command travels in a virtual channel and wherein the switch selectively couples the respective virtual channel. 
   
   
     3. The apparatus of  claim 2  wherein the switch is coupled to receive an indication from the memory bridge that the memory bridge has buffer space for a first virtual channel, and wherein the switch is to couple one of the plurality of interface circuits having a first coherency command in the first virtual channel to the memory bridge. 
   
   
     4. The apparatus of  claim 2  wherein the switch is coupled to receive an indication from a first interface circuits that the first interface circuit has buffer space for a first virtual channel, and wherein the switch is to couple the memory bridge to the first interface circuit to transmit a first coherency command in the first virtual channel. 
   
   
     5. The apparatus of  claim 1  further comprising a memory controller to couple to a memory, the memory controller coupled to the interconnect to receive transactions which access the memory, and wherein the memory bridge includes a directory which tracks coherency blocks from the memory and corresponding states in other nodes for the coherency blocks. 
   
   
     6. The apparatus of  claim 1  wherein the interconnect, the coherent agents, the plurality of interface circuits, the memory bridge, and the switch are integrated onto a same integrated circuit. 
   
   
     7. A method comprising:
 generating an intranode coherency transaction between coherent agents within a node coupled to an internal interconnect, in which the interconnect supports the intranode coherency transaction within the node with the coherent agents; 
 generating an internode coherency transaction between one of the coherent agents within the node and a remote node of a plurality of remote nodes through one of a plurality of interface circuits coupled to communicate the coherency transaction, and in which a memory bridge is coupled to the interconnect to maintain internode coherency between the one coherent agent and the remote node; 
 generating additional coherency commands in the memory bridge responsive to the coherent transaction, the memory bridge including an address map to map a node number associating a remote node with one of the interface circuits for communication of the coherency transaction from the memory bridge, via the one associated interface circuit, to the remote node; and 
 switching the one associated interface circuit to the memory bridge to selectively couple the associated interface circuit to the memory bridge for transfer of the coherency transaction.