Memory cell structure of metal programmable read only memory having bit cells with a shared transistor cell

Abstract

A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

1. A memory cell structure for a two-bit cell of a programmable ROM, comprising:
 a word line; 
 a bit line; 
 a grounding line; 
 first and second virtual grounding lines; and 
 a transistor having a controlling terminal connected to the word line, a first controlled terminal connected to the bit line and a second controlled terminal selectively floated or connected to one of the grounding line, the first virtual grounding line, the second virtual grounding line or the bit line based on values of the two bits programmed into the two-bit cell. 
 
   
   
     2. The memory cell structure of  claim 1 , wherein the second controlled terminal of the transistor is floated or connected to the bit line to program both bit values to a first logic value. 
   
   
     3. The memory cell structure of  claim 2 , wherein the second controlled terminal is connected to the grounding line to program both bit values to a second logic value opposite the first logic value. 
   
   
     4. The memory cell structure of  claim 3 , wherein the second controlled terminal is connected to the first virtual grounding line to program a value of the first bit to the second logic value and the value of the second bit to the first logic value or connected to the second virtual grounding line to program a value of the first bit to the first logic value and the value of the second bit to the second logic value. 
   
   
     5. The memory cell structure of  claim 1 , wherein the second controlled terminal is selectively floated or connected to one of the grounding line, the first virtual grounding line, the second virtual grounding line or the bit line by a metal fabrication process.