Method of manufacturing a flash memory device

Abstract

A method of manufacturing a flash memory device includes the steps of forming a tunnel oxide layer and a polysilicon layer over a semiconductor substrate. An etch process is then performed to form a pattern and a trench. An isolation layer is formed in the trench. A polysilicon spacer layer is formed on the resulting surface. A specific region of the polysilicon spacer layer and the isolation layer is etched in a single etch process to form a recess hole in a central portion of the isolation layer. The polysilicon spacer layer is then removed.

1. A method of manufacturing a flash memory device, comprising:
 forming a tunnel oxide layer and a polysilicon layer over a semiconductor substrate and then performing an etch process to form a pattern and a trench; 
 forming an isolation layer in the trench; 
 forming a spacer layer on an exposed surface of the polysilicon layer; 
 etching an exposed portion of the isolation layer using the spacer layer as a mask to form a recess hole in a central portion of the isolation layer; and 
 removing the spacer layer. 
 
   
   
     2. The method of  claim 1 , wherein the isolation layer has a height of 100 Angstroms to 600 Angstroms measured from the bottom of the tunnel oxide layer to the top of the isolation layer. 
   
   
     3. The method of  claim 1 , wherein the spacer layer is selected from the group consisting of amorphous-carbon layers, low-k materials, and oxide layers. 
   
   
     4. The method of  claim 1 , wherein removing the spacer layer comprises performing a plasma etch method to remove a photoresist by using one selected from the group consisting of O 2 , N 2 , H 2 , and combinations thereof. 
   
   
     5. The method of  claim 3 , wherein the spacer layer comprises undoped silicate glass (USG). 
   
   
     6. The method of  claim 3 , wherein the spacer layer comprises the amorphous-carbon layer and etching to form a recess hole comprises performing a dry etch process. 
   
   
     7. The method of  claim 6 , wherein the dry etch process comprises using one selected from the group consisting of SF 6 , NF 3 , CF 4 , fluorocarbon-based C x F y  compounds, fluoro-hydrocarbon-based C x H y F z  compounds, C 1   2 , BCl 3 , HBr, Hl, and combinations thereof. 
   
   
     8. The method of  claim 6 , wherein the recess hole has a bottom depth of −300 Angstroms to 300 Angstroms relative to an active top of the semiconductor substrate and a width of 100 Angstroms to 500 Angstroms. 
   
   
     9. The method of  claim 7 , wherein the dry etch process further comprises using one selected from the group consisting of O 2 , N 2 , CO, H 2 , and combinations thereof to control the etch rate and the resulting etch shape of the dry etch process.