Method of manufacturing a chip

Abstract

Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.

1. A method of manufacturing a chip, comprising:
 (a) depositing a seed metal layer on an entire upper surface of a wafer on which at least one pad is formed, the seed metal layer being deposited over the at least one pad; 
 (b) lapping a lower portion of the wafer forming an exposed wafer bottom so that the wafer has a predetermined thickness and then forming a via hole forming pattern on the exposed wafer bottom; 
 (c) etching the wafer to expose the bottom of the pad using the via hole forming pattern as an etching mask to form a via hole; and 
 (d) forming a plated metal layer to protrude up to a predetermined thickness from the bottom of the wafer in the via hole to contact the exposed bottom of the pad and then removing the seed metal layer and the via hole forming pattern. 
 
   
   
     2. The method of  claim 1 , wherein the seed metal layer is deposited by a sputtering technique using titanium/copper (Ti/Cu). 
   
   
     3. The method of  claim 2 , wherein the titanium/copper has a thickness of 400 Å to 600 Å and 2000 Å to 4000 Å, respectively. 
   
   
     4. The method of  claim 1 , wherein in step (b), the predetermined thickness of the wafer is 100 μm to 400 μm. 
   
   
     5. The method of  claim 1 , wherein step (b) comprises
 (b-1) lapping the lower portion of the wafer to have a predetermined thickness, and then sequentially forming an oxide layer and a photoresist on the exposed wafer; 
 (b-2) etching the photoresist to form a photoresist pattern for forming the via hole; and 
 (b-3) etching the oxide layer using the photoresist pattern as an etching mask, and then removing the photoresist pattern to form a via hole forming pattern. 
 
   
   
     6. The method of  claim 5 , wherein in step (b-3), the oxide layer is dry-etched using CF 4  or CHF 3 . 
   
   
     7. The method of  claim 1 , wherein in step (c), the via hole is formed by a dry etching technique using one of C 4 F 8 , SF 6 , and BCl 3  gases. 
   
   
     8. The method of  claim 1 , wherein in step (d), the metal layer is formed such that a first metal layer is formed by an electroplating technique to have a predetermined thickness from the bottom of the pad using a copper and a second metal layer is formed by an electroplating technique on the first metal layer to protrude up to a predetermined thickness from the bottom of the wafer using one of stannum/copper (Sn/Cu), stannum (Sn) and stannum/bismuth (Sn/Bi).