Hard disk drive cache memory and playback device

Abstract

A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto.

1. A controller circuit comprising:
 a first plurality of ports for connecting to a first plurality of buses for receiving and providing signals therefrom, and a second plurality of ports for connecting to a second plurality of buses for receiving and providing signals therefrom; 
 a third port for connecting to a memory; 
 said controller circuit operable in one of two modes: wherein in a first mode, said controller circuit functions as a pass through device to provide signals transparently to and from the plurality of first buses to the plurality of second buses; and wherein in a second mode, said controller circuit functions to monitor signals from one of the second plurality of buses to another of said second plurality of buses, in response to said signals requesting data from said controller circuit wherein said controller circuit analyzes said signals to determine if said data is in said memory. 
 
     
     
       2. A controller circuit comprising:
 a first plurality of ports for connecting to a first plurality of buses for receiving and providing signals therefrom; and a second plurality of ports for connecting to a second plurality of buses for receiving and providing signals therefrom; 
 a third port for connecting to a memory; 
 said controller circuit operable in one of two modes: wherein in a first mode, said controller circuit functions as a pass through device to provide signals transparently to and from the plurality of first buses to the plurality of second buses; and wherein in a second mode, said controller circuit functions to trap signals from one of the second plurality of buses and analyzes said signal to determine whether to transmit said signal to another of said second plurality of buses, in response to said signals requesting data from said controller circuit, wherein said controller circuit analyzes said signals to determine if said data is in said memory. 
 
     
     
       3. The controller circuit of  claim 1  wherein said memory is a non-volatile memory. 
     
     
       4. The controller circuit of  claim 2  wherein said memory is a non-volatile memory. 
     
     
       5. A memory device comprising:
 a first plurality of ports for connecting to a first plurality of buses for receiving and providing signals therefrom, and a second plurality of ports for connecting to a second plurality of buses for receiving and providing signals therefrom; 
 said memory device operable in one of two modes: wherein in a first mode, said memory device functions as a pass through device to provide said signals transparently to and from the plurality of first buses from and to the plurality of second buses; and wherein in a second mode, said device functions to monitor said signals from one of the second plurality of buses directed to one of said first plurality of buses, wherein said signals request data from said one of said first plurality of buses, and wherein said memory device serves to respond to said signals in the event said data requested is in said memory device. 
 
     
     
       6. A memory device comprising:
 a first plurality of ports for connecting to a first plurality of buses for receiving and providing signals therefrom, and a second plurality of ports for connecting to a second plurality of buses for receiving and providing signals therefrom; 
 said memory device operable in one of two modes: wherein in a first mode, said memory device functions as a pass through device to provide said signals transparently to and from the plurality of first buses from and to the plurality of second buses; and wherein in a second mode, said device functions to trap said signals from one of the second plurality of buses directed to one of said first plurality of buses, wherein said signals request data from said first plurality of buses, and wherein said memory device serves to re-transmit said signals after an analysis of whether said data requested is in said memory device.