IO self test method and apparatus for memory

Abstract

A memory includes a data generator to generate a data pattern, a transmitter in communication with the data generator, the transmitter to transmit the data pattern as a test data pattern, receiver to receive the test data pattern from the transmitter, and a comparator coupled with the receiver, the comparator to compare the data pattern with the test data pattern from the receiver and to verify proper operation of a memory channel. A method includes providing a seed value to a transmit and a receive pattern generator in a memory, generating data at the transmit pattern generator from the seed value and transmitting the data from the memory, looping the data to a receiver on the memory, using the seed value to generate data with the receive pattern generator, and comparing the data from the receive pattern generator and the transmit pattern generator to determine if any errors occurred.

1. An apparatus comprising:
 a first data generator to generate a test data pattern; 
 a transmitter in communication with the first data generator, the transmitter to transmit the test data pattern; 
 a multiplexer coupled between the first data generator and the transmitter to pass the data pattern to be received by the transmitter; 
 a receiver to receive the test data pattern after it has been transmitted by the transmitter; 
 a second data generator to generate a second data pattern; 
 a comparator coupled with the receiver, the comparator to compare the second data pattern with the test data pattern from the receiver and to verify proper operation of a memory channel, wherein a start delimiter is used to delay the comparison to allow for delay in transmitting and receiving the test data pattern; 
 a length counter to count a length of the test data pattern; and 
 a round trip delay counter to time the delay between transmitting the test data pattern and receiving the test data pattern, wherein a number of clocks between a transmission and receipt of the start delimiter is counted by round trip delay counter; 
 wherein the multiplexer selectively passes the received test data pattern to be re-transmitted by the transmitter. 
 
   
   
     2. The apparatus of  claim 1  wherein the first data generator includes a linear feedback shift register to generate the test data pattern from a seed value. 
   
   
     3. The apparatus of  claim 1 , further comprising:
 a serializer to serialize the test data pattern and provide the test data pattern in serialized form to the transmitter; and 
 a deserializer to deserialize the test data pattern received by the receiver and provide the deserialized test data pattern to the comparator and to the multiplexer, wherein the multiplexer selectively passes the received deserialized test data pattern to the serializer. 
 
   
   
     4. The apparatus of  claim 1 , further comprising a first memory to receive the test data pattern and to provide a return of the test data pattern to the receiver. 
   
   
     5. The apparatus of  claim 4 , further comprising a second memory to receive the test data pattern from the first memory, wherein the second memory is to provide a return of the test data pattern to the first memory, which then provides a return of the data test pattern from the second memory to the receiver. 
   
   
     6. The apparatus of  claim 1 , further comprising a first memory chip and a second memory chip, wherein the first memory chip is to receive the test data pattern from the transmitter and provide it to the second memory chip which is to provide the test data pattern back to the first memory chip which then provides it to the receiver.