Dual-gate transistor display

Abstract

A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.

1. A dual-gate thin-film transistor (DG-TFT) voltage storage circuit, the circuit comprising:
 a voltage storage element having an input, and an output; 
 a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element input, and a bottom gate connected to a bias line; and, 
 a voltage shifter having an input connected to the first gate line to accept a voltage, and an output to supply a bias voltage on the bias line, different than the voltage on the first gate line. 
 
   
   
     2. The circuit of  claim 1  wherein the DG-TFT bottom gate is aligned in a first horizontal plane;
 wherein the first S/D region and second S/D region are aligned in a second horizontal plane, overlying the first plane; 
 wherein the top gate is aligned in a third horizontal plane, overlying the second plane; and, 
 wherein the DG-TFT further comprises: 
 a channel region in the second horizontal plane, intervening between the first and second S/D regions. 
 
   
   
     3. The circuit of  claim 2  wherein the bottom gate has vertical sides; and,
 the DG-TFT further comprising: 
 insulating sidewalls over the bottom gate vertical sides; and, 
 wherein the first and second S/D regions overlie the bottom gate, between the bottom gate vertical sides. 
 
   
   
     4. The circuit of  claim 1  wherein the first gate line accepts an OFF voltage;
 wherein the voltage shifter supplies a first bias voltage; and, 
 wherein the leakage current through the DG-TFT decreases in response to the first bias voltage. 
 
   
   
     5. The circuit of  claim 1  wherein the data line accepts an analog voltage;
 wherein the first gate line accepts an ON voltage; 
 wherein the voltage shifter supplies a second bias voltage; and, 
 wherein the voltage threshold of the DG-TFT decreases in response to the second bias voltage. 
 
   
   
     6. The circuit of  claim 1  wherein the voltage storage element is selected from the group comprising a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel. 
   
   
     7. The circuit of  claim 1  wherein the voltage storage element is an LC pixel comprising:
 an LC element having a first terminal connected to the DG-TFT second S/D region, and a second terminal connected to a reference voltage; and, 
 a storage capacitor having a first terminal connected to the DG-TFT second S/D region, and a second terminal connected to a second gate line, adjacent the first gate line. 
 
   
   
     8. A dual-gate thin-film transistor (DG-TFT) voltage storage matrix, the matrix comprising:
 a plurality of data lines; 
 a plurality of gate lines; 
 a plurality of bias lines, each bias line being associated with a corresponding gate line; 
 a plurality of voltage shifters, each voltage shifter having an input connected to a corresponding gate line and an output to supply a bias voltage on a corresponding bias line, different than the voltage on the corresponding rate line; and, 
 a plurality of DG-TFT voltage storage circuits, with a unique circuit intervening between each data line and each gate line, each circuit comprising:
 a voltage storage element having an input, and an output; and, 
 a DG-TFT haying a first source/drain (S/D) connected to a data line, a top gate connected to a gate line, a second S/D region connected to the voltage storage element input, and a bottom gate connected to a bias line. 
 
 
   
   
     9. The matrix of  claim 8  wherein the DG-TFT bottom gate is aligned in a first horizontal plane;
 wherein the first S/D region and second S/D region are aligned in a second horizontal plane, overlying the first plane; 
 wherein the top gate is aligned in a third horizontal plane, overlying the second plane; and, 
 wherein the DG-TFT further comprises: 
 a channel region in the second horizontal plane, intervening between the first and second S/D regions. 
 
   
   
     10. The matrix of  claim 9  wherein the bottom gate has vertical sides; and,
 the DG-TFT further comprising: 
 insulating sidewalls over the bottom gate vertical sides; and, 
 wherein the first and second S/D regions overlie the bottom gate, between the bottom gate vertical sides. 
 
   
   
     11. The matrix of  claim 8  wherein a first gate line accepts an OFF voltage;
 wherein a first voltage shifter, connected to the first gate line, supplies a first bias voltage; and, 
 wherein the leakage current through a first DG-TFT, connected to the first data line and the first gate line, decreases in response to the first bias voltage. 
 
   
   
     12. The matrix of  claim 8  wherein a first data line accepts an analog voltage;
 wherein a first gate line accepts an ON voltage; 
 wherein a first voltage shifter, connected to the first gate line, supplies a second bias voltage; and, 
 wherein the threshold voltage of a first DG-TFT, connected to the first data line and the first gate line, decreases in response to the second bias voltage. 
 
   
   
     13. The matrix of  claim 8  wherein the voltage storage element is selected from the group including a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel. 
   
   
     14. The matrix of  claim 8  wherein the matrix is an LC display (LCD);
 wherein the voltage storage element is an LC pixel comprising:
 an LC element having a first terminal connected to the DG-TFT second S/D region, and a second terminal connected to a reference voltage; and, 
 a storage capacitor having a first terminal connected to the DG-TFT second S/D region, and a second terminal connected to a gate line, adjacent the DG-TFT gate line. 
 
 
   
   
     15. A method for controlling a dual-gate thin-film transistor (DG-TFT) voltage storage circuit, the method comprising:
 supplying a circuit with a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a gate line, a second S/D region connected to the voltage storage element, a bottom gate connected to a bias line, and a voltage shifter to accept a voltage on the gate line and to supply a voltage to the bias line, different than the voltage on the gate line; 
 supplying an OFF voltage to the gate line; 
 in response to the OFF voltage, disabling current through the DG-TFT to the voltage storage element; 
 supplying a first bias voltage to the bias line; and, 
 decreasing the leakage current through the DG-TFT in response to the first bias voltage. 
 
   
   
     16. The method of  claim 15  further comprising:
 supplying an analog voltage to the data line; 
 supplying an ON voltage to the gate line; 
 enabling current flow through the DG-TFT to the voltage storage element; 
 supplying a second bias voltage to the bias line; and, 
 decreasing the threshold voltage of the DG-TFT in response to the second bias voltage. 
 
   
   
     17. The method of  claim 16  wherein supplying the first bias voltage includes converting the gate OFF voltage to the first bias voltage; and,
 wherein supplying the second bias voltage includes converting the gate ON voltage to the second bias voltage. 
 
   
   
     18. The method of  claim 15  wherein supplying the circuit with the voltage storage element includes supplying a voltage storage element selected from the group comprising a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.