Logic circuit

Abstract

A first current source generating a current I 0 +I when a control signal is in ‘H’ level and a current I 0 when it is in ‘L’ level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second current source connected to the second transistor and generating I 0 +I are provided. Further, a node branched from a connection node between the second transistor and the second current source is formed, and a logic unit including a flip-flop circuit formed of a differential amplifier is driven through the node. The logic unit is in an active state when the control signal is in ‘H’ level and it is in an inactive state when the signal is in ‘L’ level. When the logic unit is in an active state, it processes a data input signal to generate data output signal.

1. A logic circuit, comprising:
 a current signal generating circuit which generates a current signal changing between a first current and a second current smaller than said first current in accordance with alternate voltage level change of a control signal between a first voltage level and a second voltage level; 
 a common constant current source generating a third current; 
 a current mirror circuit which transfers the current generated in said current signal generating circuit to a transistor element which is connected between a voltage source node and a common node connected to said common constant current source; and 
 a logic unit connected in parallel to said transistor element of the current mirror current, 
 wherein the parallel connection of said logic unit and said transistor element of the current mirror circuit causes limitation on current supplied to said logic unit, 
 wherein said logic unit is put into an active state by being supplied with a current corresponding to a residual obtained by subtracting said second current from said third current when said control signal is the first voltage level, and 
 wherein said logic unit is put into an inactive state due to deprivation of the supplied current which is limited to a current corresponding to residual obtained by subtracting said first current from said third current when said control is a second voltage level; 
 a logic output data is generated by processing a logic input data when said logic unit is in said active state. 
 
   
   
     2. The logic circuit according to  claim 1 , wherein said current mirror circuit is composed of MOS transistors, and
 wherein said second current is set to have a current value in a range where Vgs-Ids characteristics of said MOS transistors form a linear region. 
 
   
   
     3. The logic circuit according to  claim 1 , wherein said current signal generating circuit includes:
 a first current source which is connected to said current mirror circuit and generates said second current; 
 a switching element which has one end connected to said current mirror circuit and is turned on/off in accordance with said control signal; and 
 a second current source which is connected to the other end of said switching element and generates a fourth current, and 
 a current obtained by adding said second current and said fourth current corresponds to said first current. 
 
   
   
     4. The logic circuit according to  claim 2 , wherein said logic unit includes: a differential amplifier having transistors to be a differential pair, and
 a common node of the transistors to be a differential pair is driven by said fourth current corresponding to residual obtained by subtracting said second current from said third current when said control signal is the first voltage level. 
 
   
   
     5. A logic circuit, comprising:
 a first current signal generating circuit to which a clock signal is inputted and which generates a first current in accordance with a first voltage level of said clock signal and a second current smaller than said first current in accordance with a second voltage level thereof; 
 a first constant current source generates a third current; 
 a first current mirror circuit which has a first transfer source node element connected to said first current signal generating circuit and a first transistor element which is connected between a voltage source node and first common node connected to said first constant current source; 
 a second current signal generating circuit to which an inverted clock signal of said clock signal is inputted and which generates said first current in accordance with said first voltage level of said inverted clock signal and said second current in accordance with said second voltage level thereof; 
 a second constant current source generates a current equal to said third current; 
 a second current mirror circuit which has a second transfer source node element connected to said second current signal generating circuit and a second transistor element which is connected between said voltage source node and a second common node connected to said second constant current source, and 
 a flip-flop block including a data intake circuit connected in parallel to said first transistor element of the first current mirror circuit and a data latch circuit connected in parallel to said second transistor element of the second current mirror circuit, 
 wherein said data intake circuit includes: 
 a first transistor and a second transistor which form a differential pair and each of which has a gate to which a logic data to be a complementary signal is inputted; 
 a first load element connected to between said voltage source node and a drain of said first transistor; and 
 a second load element connected to a drain of said second transistor, 
 wherein said data latch circuit includes: 
 a third transistor having a drain connected to the drain of said first transistor; and 
 a fourth transistor having a drain connected to the drain of said second transistor, 
 sources of said first and second transistors are connected to a connection node between said first current mirror circuit and said first constant current source, and 
 sources of said third and fourth transistors are connected to said first common node connected to said second constant current source. 
 
   
   
     6. The logic circuit according to  claim 5 , wherein said first transfer source element of the first current mirror circuit includes:
 a fifth transistor having a drain connected to said first current signal generating circuit and a gate and a drain connected in common, and 
 wherein said transistor element of the first current mirror circuit includes a sixth transistor having a drain connected to said first constant current source and a gate connected to the gate of said fifth transistor, 
 wherein said transfer source element of the second current mirror circuit includes: 
 a seventh transistor having a drain connected to said second current signal generating circuit and a gate and a drain connected in common, and 
 wherein said transistor element of the second current mirror circuit includes an eighth transistor having a drain connected to said second constant current source and a gate connected to the gate of said seventh transistor, 
 wherein said second current is set to have a current value in a range where Vgs-Ids characteristics of said sixth and eighth transistors form a linear region, and 
 wherein said third current is set to have a current value almost equal to a current value obtained by transferring said first current through said first current mirror circuit and/or said second current mirror circuit. 
 
   
   
     7. The logic circuit according to  claim 6 ,
 wherein a gate of said third transistor is connected to a drain of said second transistor, and 
 a gate of said fourth transistor is connected to a drain of said first transistor. 
 
   
   
     8. The logic circuit according to  claim 6 , wherein said first current signal generating circuit includes:
 a third constant current source which is connected to a drain of said fifth transistor and generates said second current; and 
 a ninth transistor having a drain connected to the drain of said fifth transistor and a gate to which said clock signal is inputted, 
 wherein said second current signal generating circuit includes: 
 a fourth constant current source which is connected to a drain of said seventh transistor and generates said second current; and 
 a tenth transistor having a drain connected to the drain of said seventh transistor and a gate to which said inverted clock signal is inputted, 
 sources of said ninth and tenth transistors are connected in common to a fifth constant current source which generates a fourth current, and 
 a value obtained by adding said second current and said fourth current corresponds to said first current. 
 
   
   
     9. A logic circuit, comprising:
 a first current signal generating circuit to which a first control signal is inputted and which generates a first current in accordance with a first voltage level of said first control signal and a second current smaller than said first current in accordance with a second voltage level thereof; 
 a first current mirror circuit which has a first transfer source node connected to said first current signal generating circuit and a first transistor node; 
 a first constant current source which is connected to said first transistor node of said first current mirror circuit and generates a third current; 
 a second current signal generating circuit to which a second control signal is inputted and which generates said first current in accordance with said first voltage level of said second control signal and said second current in accordance with said second voltage level thereof; 
 a second current mirror circuit which has a second transfer source node connected to said second current signal generating circuit and a second transistor node; 
 a second constant current source which is connected to said second transistor node of said second current mirror circuit and generates said third current; and 
 a selector block including a first selector logic unit and a second selector logic unit, 
 wherein said first selector logic unit includes: 
 a first transistor having a gate to which a first logic data is inputted; 
 a second transistor having a gate to which a first inverted logic data which is an inverted signal of said first logic data is inputted; 
 a first load element connected to a drain of said first transistor; and 
 a second load element connected to a drain of said second transistor, 
 wherein said second selector logic unit includes: 
 a third transistor having a gate to which a second logic data is inputted and a drain connected to the drain of said first transistor; and 
 a fourth transistor having a gate to which a second inverted logic data which is an inverted data of said second logic data is inputted and a drain connected to the drain of said second transistor, 
 sources of said first and second transistors are connected to a connection node between said first current mirror circuit and said first constant current source, and 
 sources of said third and fourth transistors are connected to a connection node between said second current mirror circuit and said second constant current source. 
 
   
   
     10. The logic circuit according to  claim 9 , wherein said first current mirror circuit includes:
 a fifth transistor having a drain connected to said first current signal generating circuit and a gate and a drain connected in common; and 
 a sixth transistor having a drain connected to said first constant current source and a gate connected to a gate of said fifth transistor, 
 wherein said second current mirror circuit includes: 
 a seventh transistor having a drain connected to said second current signal generating circuit and a gate and a drain connected in common; and 
 an eighth transistor having a drain connected to said second constant current source and a gate connected to a gate of said seventh transistor, 
 wherein said second current is set to have a current value in a range where Vgs-Ids characteristics of said sixth and eighth transistors form a linear region, and 
 wherein said third current is set to have a current value almost equal to a current value obtained by transferring said first current through said first current mirror circuit and/or said second current mirror circuit.