Methods and systems for comparing currents using current conveyor circuitry

Abstract

Methods and systems are provided for comparing currents. The method includes driving a first current through a first X leg of a first current conveyor circuit and a second current through a second X leg of a second current conveyor circuit. The method further includes draining a third current from a first X terminal of the first current conveyor circuit to produce a first positive transistor current and a first negative transistor current, and draining a fourth current from a second X terminal of the second current conveyor circuit to produce a second positive transistor current and a second negative transistor current. The method further includes summing the first positive transistor current and the second negative transistor current to produce a first current output, the first negative transistor current and the second positive transistor current to produce a second current output, and the first current output and the second current output to produce a summed current output.

1. In a circuit comprising a first current conveyor circuit including a first X leg that includes a first X terminal, and a second current conveyor circuit including a second X leg that includes a second X terminal, a method for comparing currents, the method comprising:
 driving a first current through the first X leg; 
 driving a second current through the second X leg; 
 draining a third current from the first X terminal to produce a first positive transistor current and a first negative transistor current; 
 draining a fourth current from the second X terminal to produce a second positive transistor current and a second negative transistor current; 
 summing the first positive transistor current and the second negative transistor current to produce a first current output; 
 summing the first negative transistor current and the second positive transistor current to produce a second current output; and 
 summing the first current output and the second current output to produce a summed current output. 
 
   
   
     2. The method of  claim 1 :
 wherein the first current conveyor circuit includes a first positive transistor and a first negative transistor; 
 wherein the second current conveyor circuit includes a second positive transistor and a second negative transistor; 
 wherein draining the third current includes the first positive transistor producing the first positive transistor current and the first negative transistor producing the first negative transistor current; and 
 wherein draining the fourth current includes second positive transistor producing the second positive transistor current and the second negative transistor producing the second negative transistor current. 
 
   
   
     3. The method of  claim 2 , wherein draining the third current comprises draining a current above a threshold current ratio from the first X terminal to turn off the first negative transistor, and wherein, when the first negative transistor turns off, the first negative transistor current is a zero current and the second current output is a non-zero current. 
   
   
     4. The method of  claim 2 , wherein draining the fourth current comprises draining a current above a threshold current ratio from the second X terminal to turn off the second negative transistor, and wherein, when the second negative transistor turns off, the second negative transistor current is a zero current and the first current output is a non-zero current. 
   
   
     5. The method of  claim 1 , wherein:
 summing the first positive transistor current and the second negative transistor current to produce a first current output comprises an adder summing the first positive transistor current and the second negative transistor current; 
 summing the first negative transistor current and the second positive transistor current to produce a second current output comprises the adder summing the first negative transistor current and the second positive; and 
 summing the first current output and the second current output to produce a summed current output comprises the adder summing the first current output and the second current output. 
 
   
   
     6. The method of  claim 1 , wherein the circuit includes a differential amplifier that includes a first current load input and a second current load input, the method further comprising, coupling the first current output to the first current load input and coupling the second current output to the second current load input to cooperatively produce a first voltage output corresponding to the first current output and a second voltage output corresponding to the second current output. 
   
   
     7. The method of  claim 6 , wherein the differential amplifier includes a reference current input, the method further comprising, connecting the summed current output to the reference current input to hold an average of the first voltage output and the second voltage output substantially constant. 
   
   
     8. The method of  claim 6 , further comprising comparing the first voltage output to the second voltage output to provide an indication of whether the first current output is greater than the second current output. 
   
   
     9. The method of  claim 1 , wherein the first current conveyor circuit comprises a first Y leg that includes a first Y terminal, wherein a first reference voltage is applied to the first Y terminal, the method further comprising, holding the first reference voltage substantially constant by coupling a first inverter to the first Y terminal. 
   
   
     10. The method of  claim 1 , wherein the second current conveyor circuit comprises a second Y leg that includes a second Y terminal, wherein a second reference voltage is applied to the second Y terminal, the method further comprising, holding the second reference voltage substantially constant by coupling a second inverter to the second Y terminal. 
   
   
     11. A system for comparing currents, the system comprising:
 a first current conveyor circuit that includes a first Y leg and a first X leg, wherein the first X leg comprises a first X terminal, a first positive transistor, and a first negative transistor, wherein the first Y leg drives a first current through the first X leg, and wherein the first X terminal drains a second current such that the first positive transistor produces a first positive transistor current and the first negative transistor produces a first negative transistor current; 
 a second current conveyor circuit that includes a second Y leg and a second X leg, wherein the second X leg comprises a second X terminal, a second positive transistor, and a second negative transistor, wherein the second Y leg drives a third current through the second X leg, and wherein the second X terminal drains a fourth current such that the second positive transistor produces a second positive transistor current and the second negative transistor produces a second negative transistor current; and 
 an adder coupled to the first current conveyor circuit and the second current conveyor circuit, and operable to:
 sum the first positive transistor current and the second negative transistor current to produce a first current output; 
 sum the first negative transistor current and the second positive transistor current to produce a second current output; and 
 sum the first current output and the second current output to produce a summed current output. 
 
 
   
   
     12. The system of  claim 11 , wherein the adder is coupled to the first positive transistor, first negative transistor, second positive transistor, and second negative transistor. 
   
   
     13. The system of  claim 11 , wherein the first X terminal drains a current above a threshold current ratio to turn off the first negative transistor, and wherein, when the first negative transistor turns off, the first negative transistor current is a zero current and the second current output is a non-zero current. 
   
   
     14. The system of  claim 11 , wherein the second X terminal drains a current above a threshold current ratio to turn off the second negative transistor, and wherein, when the second negative transistor turns off, the second negative transistor current is a zero current and the first current output is a non-zero current. 
   
   
     15. The system of  claim 11 , further comprising a differential amplifier coupled to the adder, wherein the differential amplifier includes a first current load input and a second current load input, and wherein the first current output is coupled to the first current load input and the second current output is coupled to the second current load input such that the differential amplifier produces a first voltage output corresponding to the first current output and a second voltage output corresponding to the second current output. 
   
   
     16. The system of  claim 15 , wherein the differential amplifier comprises a reference current input, and wherein the summed current output is connected to the reference current input of the differential amplifier to hold an average of the first voltage output and the second voltage output substantially constant. 
   
   
     17. The system of  claim 15 , further comprising a comparator coupled to the differential amplifier, wherein the comparator compares the first voltage output and the second voltage output to provide an indication of whether the first current output is greater than the second current output. 
   
   
     18. The system of  claim 11 , wherein the first Y leg includes a first Y terminal, wherein a first reference voltage is applied to the first Y terminal, the system further comprising a first inverter coupled to the first Y terminal to hold the first reference voltage substantially constant. 
   
   
     19. The system of  claim 11 , wherein the second Y leg includes a second Y terminal, wherein a second reference voltage is applied to the second Y terminal, the system further comprising a second inverter coupled to the second Y terminal to hold the second reference voltage substantially constant. 
   
   
     20. A system for comparing currents, the system comprising:
 a first current conveyor circuit that includes a first Y leg and a first X leg, wherein the first X leg comprises a first X terminal, a first positive transistor, and a first negative transistor, wherein the first Y leg drives a first current through the first X leg, and wherein the first X terminal drains a second current such that the first positive transistor produces a first positive transistor Current and the first negative transistor produces a first negative transistor current; 
 a second current conveyor circuit that includes a second Y leg and a second X leg, wherein the second X leg comprises a second X terminal, a second positive transistor, and a second negative transistor, wherein the second Y leg drives a third current through the second X leg, and wherein the second X terminal drains a fourth current such that the second positive transistor produces a second positive transistor current and the second negative transistor produces a second negative transistor current; 
 an adder coupled to the first current conveyor circuit and the second current conveyor circuit, and operable to:
 sum the first positive transistor current and the second negative transistor current to produce a first current output; 
 sum the first negative transistor current and the second positive transistor current to produce a second current output; and 
 sum the first current output and the second current output to produce a summed current output; 
 
 a differential amplifier coupled to the adder, wherein the differential amplifier includes a first current load input, a second current load input, and reference current input, wherein the first current output is coupled to the first current load input and the second current output is coupled to the second current load input to cooperatively produce a first voltage output corresponding to the first current output and a second voltage output corresponding to the second current output, and wherein the summed current output is connected to the reference current input of the differential amplifier to hold an average of the first voltage output and the second voltage output substantially constant; and 
 a comparator coupled to the differential amplifier, wherein the comparator compares the first voltage output and the second voltage output to provide an indication of whether the first current output is greater than the second current output.