Dynamic well bias controlled by Vt detector

Abstract

The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amp is increased to in effect lower the threshold voltages for the NCH transistors so that they are more easily activated during sensing. The back bias voltage is preferably increased from ground (its normal value) to the threshold voltage of a NCH transistor (NVt), a value low enough to prevent the circuit from latch-up. Moreover, this voltage is preferably arrived at using a Vt detector/bias circuitry which receives the p- well bias voltage as feedback. While benefiting the disclosed sense amp circuit, the dynamic bias provided to the p- well of the NCH transistors can also benefit NCH transistors in other CMOS circuitry as well. Moreover, similar modifications to dynamically bias the n- wells of PCH transistors in CMOS circuits are also provided to increase the sensing margins of PCH transistors as well.

1. An integrated circuit, comprising:
 a sense amplifier at the edge of an array of memory cells, the sense amplifier coupled to a pair of complementary data lines coupled to certain of the memory cells, the sense amplifier comprising at least one transistor of a first polarity in a well, wherein the sense amplifier senses data on a data line during a first time period and does not sense data during a second time period; 
 a driver circuit for biasing the well to a first voltage during the first time period, and for biasing the well to a second voltage during the second time period, wherein the first voltage differs from the second voltage by a transistor threshold voltage. 
 
   
   
     2. The integrated circuit of  claim 1 , wherein the driver circuit receives the first voltage as feedback to maintain the first voltage to an appropriate level. 
   
   
     3. The integrated circuit of  claim 1 , wherein the at least one transistor is an N-channel transistor, and the well is a p well. 
   
   
     4. The integrated circuit of  claim 1 , wherein the first voltage is a threshold voltage of an N-channel transistor, and the second voltage is ground. 
   
   
     5. The integrated circuit of  claim 1 , wherein biasing the well to the first voltage makes the at least one transistor easier to turn on than when the well is biased to the second voltage. 
   
   
     6. The integrated circuit of  claim 1 , wherein the well is a p well inside an n well. 
   
   
     7. The integrated circuit of  claim 6 , wherein the n well is biased to an internal power source voltage for the integrated circuit, the first voltage is a threshold voltage of an N-channel transistor, and the second voltage is ground. 
   
   
     8. An integrated circuit, comprising:
 an operative circuit comprising at least one transistor of a first polarity in a well, 
 a driver circuit for selectively biasing the well to a voltage during certain time periods during the operation of the operative circuit, wherein the driver circuit receives the voltage as feedback to maintain the voltage at an appropriate level, wherein the voltage comprises a transistor threshold voltage. 
 
   
   
     9. The integrated circuit of  claim 8 , wherein the operative circuit is a sense amplifier, and wherein during the certain time periods the sense amplifier is sensing data along a column in a memory array. 
   
   
     10. The integrated circuit of  claim 8 , wherein the at least one transistor is an N-channel transistor, and the well is a p well. 
   
   
     11. The integrated circuit of  claim 8 , wherein biasing the well to the voltage makes the at least one transistor easier to turn on than when the well is not biased. 
   
   
     12. The integrated circuit of  claim 8 , wherein the driver circuit further biases the well to ground not during the certain time periods. 
   
   
     13. The integrated circuit of  claim 8 , wherein the well is a p well inside an n well. 
   
   
     14. The integrated circuit of  claim 13 , wherein the n well is biased to an internal power source voltage for the integrated circuit, and the voltage is a threshold voltage of an N-channel transistor. 
   
   
     15. A CMOS circuit, comprising:
 an n well comprising at least one P-channel transistor and a p well within the n well comprising at least one N-channel transistor, 
 wherein the p well is biased to ground during first periods of operation of the CMOS circuit, and to a transistor threshold voltage during second periods of the CMOS circuit, and 
 wherein the transistor threshold voltage is produced by a driver circuit in which the p well bias is fed back to maintain the transistor threshold voltage at an appropriate level. 
 
   
   
     16. The CMOS circuit of  claim 15 , wherein the at least one P-channel and at least one N-channel transistors comprise portions of a sense amplifier, and wherein the second periods of operation comprise sensing of data along a column in a memory array. 
   
   
     17. The CMOS circuit of  claim 15 , wherein the transistor threshold voltage is a threshold voltage of an N-channel transistor. 
   
   
     18. The CMOS circuit of  claim 15 , wherein the n well is biased to an internal power source voltage for the CMOS circuit. 
   
   
     19. A CMOS circuit, comprising:
 N-channel transistors in a p well, wherein the p well is dynamically biased by feedback to a transistor threshold voltage. 
 
   
   
     20. The CMOS circuit of  claim 19 , wherein the p well is only dynamically biased during a first time period. 
   
   
     21. The CMOS circuit of  claim 20 , wherein the p well is biased to ground outside of the first time period. 
   
   
     22. The CMOS circuit of  claim 20 , wherein the CMOS circuit is a sense amplifier, and wherein the sense amplifier is operational when sensing data along a column in a memory array. 
   
   
     23. The CMOS circuit of  claim 19 , wherein the transistor threshold voltage is a threshold voltage of an N-channel transistor. 
   
   
     24. The CMOS circuit of  claim 19 , further comprising P-channel transistors in an n well, wherein the p well is within the n well, and wherein the n well is biased to an internal power source voltage for the CMOS circuit. 
   
   
     25. A sense amplifier, comprising:
 P-channel transistors in an n well and N-channel transistors in a p well within the n well, wherein the P-channel and N-channel transistors are cross-coupled to detect data on at least one column in a memory array, 
 wherein the p well is biased to an N-channel transistor threshold voltage at least when the sense amplifier is sensing. 
 
   
   
     26. The sense amplifier of  claim 25 , wherein the p well is biased to the N-channel transistor threshold voltage only when the sense amplifier is sensing, and is otherwise biased to ground. 
   
   
     27. The sense amplifier of  claim 25 , wherein biasing the p well to the N-channel transistor threshold voltage comprises use of a detector feedback circuit for receiving the N-channel transistor threshold voltage and adjusting the N-channel transistor threshold voltage to an appropriate level. 
   
   
     28. The sense amplifier of  claim 25 , wherein the n well is biased to a power source voltage. 
   
   
     29. A method for biasing a well in a sense amplifier at the edge of an array of memory cells, the sense amplifier coupled to at least one column coupled to certain of the memory cells, the well comprising at least one transistor of a first polarity, the method comprising:
 biasing the well to a first voltage during a first time period when the sense amplifier is sensing data from the at least one column, and 
 biasing the well to a second voltage during a second time period corresponding to a precharge time period during which the sense amplifier is not sensing, wherein the first voltage differs from the second voltage by a transistor threshold voltage. 
 
   
   
     30. The method of  claim 29 , wherein biasing the well to the first voltage comprises feeding the first voltage back to a detector circuit to maintain the first voltage at an appropriate level. 
   
   
     31. The method of  claim 29 , wherein the at least one transistor is an N-channel transistor, and the well is a p well. 
   
   
     32. The method of  claim 29 , wherein the first voltage is a threshold voltage of an N-channel transistor, and the second voltage is ground. 
   
   
     33. The method of  claim 29 , wherein biasing the well to the first voltage makes the at least one transistor easier to turn on than when the well is biased to the second voltage. 
   
   
     34. The method of  claim 29 , wherein the well is a p well inside an n well. 
   
   
     35. A method for biasing a CMOS circuit, the CMOS circuit comprising an n well comprising at least one P-channel transistor and a p well within the n well comprising at least one N-channel transistor, the method comprising:
 biasing the p well to ground during first periods of operation of the CMOS circuit; and 
 biasing the p well to a transistor threshold voltage during other periods of operation of the CMOS circuit, wherein the transistor threshold voltage is maintained by a feedback circuit. 
 
   
   
     36. The method of  claim 35 , wherein the CMOS circuit is a sense amplifier, and wherein the other periods comprise sensing of data along at least one column in a memory array. 
   
   
     37. The method of  claim 35 , wherein the transistor threshold voltage is a threshold voltage of an N-channel transistor. 
   
   
     38. The method of  claim 35 , further comprising biasing then well to an internal power source voltage for the CMOS circuit.